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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 12:30:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:05:12 -0700 |
| commit | 9224b3bc1721ae45abf11594b3ab9a58e50aa86f (patch) | |
| tree | cf756810ebe070fd369d9c8ac7c5693a67f0fcb7 /tests/ice40/mux.ys | |
| parent | 388eb3288c907dbc8b2763ffc20b0b5fccba81ed (diff) | |
| download | yosys-9224b3bc1721ae45abf11594b3ab9a58e50aa86f.tar.gz yosys-9224b3bc1721ae45abf11594b3ab9a58e50aa86f.tar.bz2 yosys-9224b3bc1721ae45abf11594b3ab9a58e50aa86f.zip | |
Remove tech independent synthesis
Diffstat (limited to 'tests/ice40/mux.ys')
| -rw-r--r-- | tests/ice40/mux.ys | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 9e3d87b7f..63d22001f 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,6 +1,8 @@ read_verilog mux.v -synth_ice40 +proc +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 design -load postopt -select -assert-count 20 t:SB_LUT4 -select -assert-count 1 t:SB_CARRY +cd top +select -assert-count 19 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D |