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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 12:20:49 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 12:20:49 +0200 |
| commit | ef417fb1b3555a3075bcd01cb7c5267f3e55b407 (patch) | |
| tree | 80813ffc49a6a645cb28224af9359ebfe12634a5 /tests/efinix/logic.ys | |
| parent | 2ed2e9c3e8f2d9d6882588857c8556a6e2af57ea (diff) | |
| parent | eb750670e3835a1bad36cb604e04bf4836cc7f91 (diff) | |
| download | yosys-ef417fb1b3555a3075bcd01cb7c5267f3e55b407.tar.gz yosys-ef417fb1b3555a3075bcd01cb7c5267f3e55b407.tar.bz2 yosys-ef417fb1b3555a3075bcd01cb7c5267f3e55b407.zip | |
Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix
Diffstat (limited to 'tests/efinix/logic.ys')
| -rw-r--r-- | tests/efinix/logic.ys | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/tests/efinix/logic.ys b/tests/efinix/logic.ys new file mode 100644 index 000000000..c2a7f5169 --- /dev/null +++ b/tests/efinix/logic.ys @@ -0,0 +1,8 @@ +read_verilog logic.v +hierarchy -top top +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:EFX_LUT4 +select -assert-none t:EFX_LUT4 %% t:* %D |