From 1070f2e90b9ba37856932189ef09a0f2316d9a21 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Mon, 23 Sep 2019 15:51:41 +0300 Subject: Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. --- tests/efinix/logic.ys | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 tests/efinix/logic.ys (limited to 'tests/efinix/logic.ys') diff --git a/tests/efinix/logic.ys b/tests/efinix/logic.ys new file mode 100644 index 000000000..c2a7f5169 --- /dev/null +++ b/tests/efinix/logic.ys @@ -0,0 +1,8 @@ +read_verilog logic.v +hierarchy -top top +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:EFX_LUT4 +select -assert-none t:EFX_LUT4 %% t:* %D -- cgit v1.2.3