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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 09:04:02 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 09:04:02 +0200 |
| commit | 0d60902fd97bba4f231f8f600434b8a69562ffff (patch) | |
| tree | 4aa61553937e9434b66c66ee16ad927665ace2ce /tests/ecp5/dffs.ys | |
| parent | 7785f23719cdbcae6816415cf2dc124aba312c66 (diff) | |
| download | yosys-0d60902fd97bba4f231f8f600434b8a69562ffff.tar.gz yosys-0d60902fd97bba4f231f8f600434b8a69562ffff.tar.bz2 yosys-0d60902fd97bba4f231f8f600434b8a69562ffff.zip | |
hierarchy - proc reorder
Diffstat (limited to 'tests/ecp5/dffs.ys')
| -rw-r--r-- | tests/ecp5/dffs.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys index 93b8595ad..a4f45d2fb 100644 --- a/tests/ecp5/dffs.ys +++ b/tests/ecp5/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module |