From 0d60902fd97bba4f231f8f600434b8a69562ffff Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:04:02 +0200 Subject: hierarchy - proc reorder --- tests/ecp5/dffs.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests/ecp5/dffs.ys') diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys index 93b8595ad..a4f45d2fb 100644 --- a/tests/ecp5/dffs.ys +++ b/tests/ecp5/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module -- cgit v1.2.3