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| author | Miodrag Milanović <mmicko@gmail.com> | 2020-01-14 19:19:32 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-14 19:19:32 +0100 |
| commit | 9fbeb57bbdb98265b541d7a62213e83de63c8a1a (patch) | |
| tree | a095bc5fbcfe5a3007fc17b928887e4b9fe2cefa /tests/arch | |
| parent | ca2f3db53f3f330d283079bf44b3cef6b7f197be (diff) | |
| parent | ccfe1e5909ba6093e49ebdfaa1aac6c4aa267036 (diff) | |
| download | yosys-9fbeb57bbdb98265b541d7a62213e83de63c8a1a.tar.gz yosys-9fbeb57bbdb98265b541d7a62213e83de63c8a1a.tar.bz2 yosys-9fbeb57bbdb98265b541d7a62213e83de63c8a1a.zip | |
Merge pull request #1623 from YosysHQ/mmicko/edif_attr
Export wire properties in EDIF
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/xilinx/add_sub.ys | 8 | ||||
| -rw-r--r-- | tests/arch/xilinx/counter.ys | 7 | ||||
| -rw-r--r-- | tests/arch/xilinx/fsm.ys | 2 |
3 files changed, 8 insertions, 9 deletions
diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 313948cc5..70cfe81a3 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -4,8 +4,8 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 14 t:LUT2 -select -assert-count 6 t:MUXCY -select -assert-count 8 t:XORCY -select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D +stat +select -assert-count 16 t:LUT2 +select -assert-count 2 t:CARRY4 +select -assert-none t:LUT2 t:CARRY4 %% t:* %D diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys index 11c29922e..064519ce7 100644 --- a/tests/arch/xilinx/counter.ys +++ b/tests/arch/xilinx/counter.ys @@ -5,10 +5,9 @@ flatten equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module - +stat select -assert-count 1 t:BUFG select -assert-count 8 t:FDCE select -assert-count 1 t:INV -select -assert-count 7 t:MUXCY -select -assert-count 8 t:XORCY -select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D +select -assert-count 2 t:CARRY4 +select -assert-none t:BUFG t:FDCE t:INV t:CARRY4 %% t:* %D diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 3235d5af3..a464fcfdb 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -9,7 +9,7 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module - +stat select -assert-count 1 t:BUFG select -assert-count 4 t:FDRE select -assert-count 1 t:FDSE |