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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-02 12:32:27 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-02 12:32:27 -0800 |
| commit | 4f889b2f57b732083dd4bf336a0d361f70e5b2d0 (patch) | |
| tree | 5f8e46c0273e9e9bee1d6e6a6775b3f58ec302da /tests/arch | |
| parent | b1e248b0e6c7945870c83ac82bfb4ed8e9d8ff66 (diff) | |
| parent | 090e54569a58b26d616806337c28507d199ca43c (diff) | |
| download | yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.tar.gz yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.tar.bz2 yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.zip | |
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/ecp5/bug1630.ys | 2 | ||||
| -rw-r--r-- | tests/arch/xilinx/bug1480.ys | 18 |
2 files changed, 19 insertions, 1 deletions
diff --git a/tests/arch/ecp5/bug1630.ys b/tests/arch/ecp5/bug1630.ys index b419fb9bb..63df1ad5b 100644 --- a/tests/arch/ecp5/bug1630.ys +++ b/tests/arch/ecp5/bug1630.ys @@ -1,2 +1,2 @@ read_ilang bug1630.il.gz -abc9 -lut +/ecp5/abc9_5g.lut +abc9 -lut 4 diff --git a/tests/arch/xilinx/bug1480.ys b/tests/arch/xilinx/bug1480.ys new file mode 100644 index 000000000..84faea08a --- /dev/null +++ b/tests/arch/xilinx/bug1480.ys @@ -0,0 +1,18 @@ +read_verilog << EOF +module top(...); + +input signed [17:0] A; +input signed [17:0] B; +output X; +output Y; + +wire [35:0] P; +assign P = A * B; + +assign X = P[0]; +assign Y = P[35]; + +endmodule +EOF + +synth_xilinx |