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| author | KrystalDelusion <krystinedawn@yosyshq.com> | 2022-07-07 10:27:54 +1200 |
|---|---|---|
| committer | KrystalDelusion <krystinedawn@yosyshq.com> | 2023-02-21 05:23:15 +1300 |
| commit | af1b9c9e070dd5873871c73c5762fbefd345a8c9 (patch) | |
| tree | fb128b5f96effbfe90a8efd239da411f8052d2f7 /tests/arch/ice40/spram.ys | |
| parent | de2f140c090742ec8ccded4cfacc2dc6bac2a562 (diff) | |
| download | yosys-af1b9c9e070dd5873871c73c5762fbefd345a8c9.tar.gz yosys-af1b9c9e070dd5873871c73c5762fbefd345a8c9.tar.bz2 yosys-af1b9c9e070dd5873871c73c5762fbefd345a8c9.zip | |
Tests for ram_style = "huge"
iCE40 SPRAM and Xilinx URAM
Diffstat (limited to 'tests/arch/ice40/spram.ys')
| -rw-r--r-- | tests/arch/ice40/spram.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/arch/ice40/spram.ys b/tests/arch/ice40/spram.ys new file mode 100644 index 000000000..709c21862 --- /dev/null +++ b/tests/arch/ice40/spram.ys @@ -0,0 +1,15 @@ +read_verilog spram.v +hierarchy -top top +synth_ice40 +select -assert-count 1 t:SB_SPRAM256KA +select -assert-none t:SB_SPRAM256KA %% t:* %D + +# Testing with pattern as described in pattern document +design -reset +read_verilog spram.v +chparam -set SKIP_RDEN 0 +hierarchy -top top +synth_ice40 +select -assert-count 1 t:SB_SPRAM256KA +# Below fails due to extra SB_LUT4 +# select -assert-none t:SB_SPRAM256KA %% t:* %D |