Tests for ram_style = "huge"

iCE40 SPRAM and Xilinx URAM

2 files changed, 37 insertions, 0 deletions

diff --git a/tests/arch/ice40/spram.v b/tests/arch/ice40/spram.v
new file mode 100644
index 000000000..4e1aef2c6
--- /dev/null
+++ b/tests/arch/ice40/spram.v
@@ -0,0 +1,22 @@
+module top (clk, write_enable, read_enable, write_data, addr, read_data);
+parameter DATA_WIDTH = 8;
+parameter ADDR_WIDTH = 8;
+parameter SKIP_RDEN = 1;
+
+input clk;
+input write_enable, read_enable;
+input [DATA_WIDTH - 1 : 0] write_data;
+input [ADDR_WIDTH - 1 : 0] addr; 
+output [DATA_WIDTH - 1 : 0] read_data;
+
+(* ram_style = "huge" *)
+reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0];
+
+always @(posedge clk) begin
+	if (write_enable)
+		mem[addr] <= write_data;
+	else if (SKIP_RDEN || read_enable)
+		read_data <= mem[addr];
+end
+
+endmodule
diff --git a/tests/arch/ice40/spram.ys b/tests/arch/ice40/spram.ys
new file mode 100644
index 000000000..709c21862
--- /dev/null
+++ b/tests/arch/ice40/spram.ys
@@ -0,0 +1,15 @@
+read_verilog spram.v
+hierarchy -top top
+synth_ice40
+select -assert-count 1 t:SB_SPRAM256KA
+select -assert-none t:SB_SPRAM256KA %% t:* %D
+
+# Testing with pattern as described in pattern document
+design -reset
+read_verilog spram.v
+chparam -set SKIP_RDEN 0
+hierarchy -top top
+synth_ice40
+select -assert-count 1 t:SB_SPRAM256KA
+# Below fails due to extra SB_LUT4
+# select -assert-none t:SB_SPRAM256KA %% t:* %D