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| author | KrystalDelusion <krystinedawn@yosyshq.com> | 2022-07-05 11:18:43 +1200 |
|---|---|---|
| committer | KrystalDelusion <krystinedawn@yosyshq.com> | 2023-02-21 05:23:15 +1300 |
| commit | de2f140c090742ec8ccded4cfacc2dc6bac2a562 (patch) | |
| tree | 054160719f1315c277fdda948ada568d5c209360 /tests/arch/ecp5 | |
| parent | 48f4e0920291c3163ac9d987a62bdc6deed722f6 (diff) | |
| download | yosys-de2f140c090742ec8ccded4cfacc2dc6bac2a562.tar.gz yosys-de2f140c090742ec8ccded4cfacc2dc6bac2a562.tar.bz2 yosys-de2f140c090742ec8ccded4cfacc2dc6bac2a562.zip | |
Testing TDP synth mapping
New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
Diffstat (limited to 'tests/arch/ecp5')
| -rw-r--r-- | tests/arch/ecp5/memories.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys index 5cddcb952..f075182c8 100644 --- a/tests/arch/ecp5/memories.ys +++ b/tests/arch/ecp5/memories.ys @@ -260,3 +260,13 @@ setattr -set logic_block 1 m:memory synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:DP16KD # requested LUTROM explicitly select -assert-min 9 t:LUT4 + +# ============================== TDP RAM ============================== +# RAM bits <= 18K; Data width <= 18x2; Address width <= 9: -> DP16KD + +design -reset; read_verilog -defer ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp +hierarchy -top sync_ram_tdp +synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp +select -assert-count 1 t:DP16KD +select -assert-none t:LUT4 |