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| author | KrystalDelusion <krystinedawn@yosyshq.com> | 2022-07-05 11:18:43 +1200 |
|---|---|---|
| committer | KrystalDelusion <krystinedawn@yosyshq.com> | 2023-02-21 05:23:15 +1300 |
| commit | de2f140c090742ec8ccded4cfacc2dc6bac2a562 (patch) | |
| tree | 054160719f1315c277fdda948ada568d5c209360 | |
| parent | 48f4e0920291c3163ac9d987a62bdc6deed722f6 (diff) | |
| download | yosys-de2f140c090742ec8ccded4cfacc2dc6bac2a562.tar.gz yosys-de2f140c090742ec8ccded4cfacc2dc6bac2a562.tar.bz2 yosys-de2f140c090742ec8ccded4cfacc2dc6bac2a562.zip | |
Testing TDP synth mapping
New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
| -rw-r--r-- | tests/arch/common/blockram.v | 31 | ||||
| -rw-r--r-- | tests/arch/ecp5/memories.ys | 10 | ||||
| -rw-r--r-- | tests/arch/gatemate/memory.ys | 8 |
3 files changed, 49 insertions, 0 deletions
diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index 5ed0736d0..6b557fdca 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -45,3 +45,34 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sdp + +`default_nettype none +module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire clk_a, clk_b, + input wire write_enable_a, write_enable_b, + input wire read_enable_a, read_enable_b, + input wire [DATA_WIDTH-1:0] write_data_a, write_data_b, + input wire [ADDRESS_WIDTH-1:0] addr_a, addr_b, + output reg [DATA_WIDTH-1:0] read_data_a, read_data_b); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] mem [0:DEPTH]; + + always @(posedge clk_a) begin + if (write_enable_a) + mem[addr_a] <= write_data_a; + else + read_data_a <= mem[addr_a]; + end + + always @(posedge clk_b) begin + if (write_enable_b) + mem[addr_b] <= write_data_b; + else + read_data_b <= mem[addr_b]; + end + +endmodule // sync_ram_tdp + diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys index 5cddcb952..f075182c8 100644 --- a/tests/arch/ecp5/memories.ys +++ b/tests/arch/ecp5/memories.ys @@ -260,3 +260,13 @@ setattr -set logic_block 1 m:memory synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:DP16KD # requested LUTROM explicitly select -assert-min 9 t:LUT4 + +# ============================== TDP RAM ============================== +# RAM bits <= 18K; Data width <= 18x2; Address width <= 9: -> DP16KD + +design -reset; read_verilog -defer ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp +hierarchy -top sync_ram_tdp +synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp +select -assert-count 1 t:DP16KD +select -assert-none t:LUT4 diff --git a/tests/arch/gatemate/memory.ys b/tests/arch/gatemate/memory.ys index e919920f8..c4bf11cd3 100644 --- a/tests/arch/gatemate/memory.ys +++ b/tests/arch/gatemate/memory.ys @@ -6,6 +6,14 @@ cd sync_ram_sdp select -assert-count 1 t:CC_BUFG select -assert-count 1 t:CC_BRAM_20K +# 512 x 20 bit x 2 -> CC_BRAM_20K TDP RAM +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 20 sync_ram_tdp +synth_gatemate -top sync_ram_tdp -noiopad +select -assert-count 2 t:CC_BUFG +select -assert-count 1 t:CC_BRAM_20K + # 512 x 80 bit -> CC_BRAM_40K SDP RAM design -reset read_verilog ../common/blockram.v |