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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 19:59:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 19:59:24 -0700 |
| commit | 7899a06ed64c55e8d804ef2970ad983e3d112013 (patch) | |
| tree | 9a73edcb4fe34d9be9fc79e44a751d16cd29c1e0 /techlibs | |
| parent | ad35b509de55df1ab5c6a360adec1e3777ba2410 (diff) | |
| download | yosys-7899a06ed64c55e8d804ef2970ad983e3d112013.tar.gz yosys-7899a06ed64c55e8d804ef2970ad983e3d112013.tar.bz2 yosys-7899a06ed64c55e8d804ef2970ad983e3d112013.zip | |
Another typo
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index 91cfbc4c4..6f9011ef1 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -94,7 +94,7 @@ module FDPE (output reg Q, input C, CE, D, PRE); parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; wire \$nextQ , \$currQ ; - \$__ABC_FDCE #( + \$__ABC_FDPE #( .INIT(|0), .IS_C_INVERTED(IS_C_INVERTED), .IS_D_INVERTED(IS_D_INVERTED), |