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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 19:05:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 19:05:53 -0700 |
| commit | ad35b509de55df1ab5c6a360adec1e3777ba2410 (patch) | |
| tree | c75d7059dc512c6473889c5c8adb46e569a87da1 /techlibs | |
| parent | e603d719d650722e4fcd1b65b46c64da19c92f81 (diff) | |
| download | yosys-ad35b509de55df1ab5c6a360adec1e3777ba2410.tar.gz yosys-ad35b509de55df1ab5c6a360adec1e3777ba2410.tar.bz2 yosys-ad35b509de55df1ab5c6a360adec1e3777ba2410.zip | |
Another typo
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index 96cbb1e04..91cfbc4c4 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -68,7 +68,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); ); \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); generate - if (IS_PRE_INVERTED) + if (IS_CLR_INVERTED) \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q)); else \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b0), .B(\$currQ ), .S(CLR), .Y(Q)); |