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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-18 11:03:38 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 3b74e0fa45a93f23448215ef9148ddc7bcd78cd7 (patch) | |
| tree | 652a8750d9d7a7bf7916198e1bff6a801fd6e9cd /techlibs/xilinx | |
| parent | 6bb3d9f9c09993960a5a91fa51f163a7e67e2503 (diff) | |
| download | yosys-3b74e0fa45a93f23448215ef9148ddc7bcd78cd7.tar.gz yosys-3b74e0fa45a93f23448215ef9148ddc7bcd78cd7.tar.bz2 yosys-3b74e0fa45a93f23448215ef9148ddc7bcd78cd7.zip | |
xilinx: add delays to INV
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 0896f3176..df3b554c1 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -160,6 +160,9 @@ module INV( input I ); assign O = !I; + specify + (I => O) = 127; + endspecify endmodule (* abc9_lut=1 *) |