diff options
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 0896f3176..df3b554c1 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -160,6 +160,9 @@ module INV( input I ); assign O = !I; + specify + (I => O) = 127; + endspecify endmodule (* abc9_lut=1 *) |