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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-17 20:48:40 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-17 20:48:40 +0200 |
| commit | c20571ca5e908d8fe85e41c1632e84de582dc68b (patch) | |
| tree | d998b4ff1708cc42fec869071ea322f0c361170c /techlibs/xilinx7 | |
| parent | f5c0ed6c79010df60cdb7ab3ea4c26ed3d61e2f1 (diff) | |
| download | yosys-c20571ca5e908d8fe85e41c1632e84de582dc68b.tar.gz yosys-c20571ca5e908d8fe85e41c1632e84de582dc68b.tar.bz2 yosys-c20571ca5e908d8fe85e41c1632e84de582dc68b.zip | |
Avoid re-arranging signals on register outputs
Diffstat (limited to 'techlibs/xilinx7')
0 files changed, 0 insertions, 0 deletions