iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Renamed techlibs/xilinx7 to techlibs/xilinx	Clifford Wolf	2013-10-26	8	-316/+0
*	Improved xilinx mojo_counter example	Clifford Wolf	2013-10-26	2	-2/+5
*	Added another xilinx example (not funcional yet)	Clifford Wolf	2013-10-26	4	-0/+101
*	Added map, par and bitgen to xlinx7 example	Clifford Wolf	2013-10-16	1	-2/+39
*	Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)	Clifford Wolf	2013-08-27	1	-2/+10
*	Added simple xilinx7 technology mapping files	Clifford Wolf	2013-08-22	4	-0/+167