From 13fa873f11c8332a10c1dda9e42c62b20e93c6b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 28 Aug 2019 15:28:01 +0000 Subject: Use extractinv for synth_xilinx -ise --- techlibs/xilinx/xc7_brams_bb.v | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'techlibs/xilinx/xc7_brams_bb.v') diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v index 5b40a457d..a28ba5b14 100644 --- a/techlibs/xilinx/xc7_brams_bb.v +++ b/techlibs/xilinx/xc7_brams_bb.v @@ -2,16 +2,24 @@ module RAMB18E1 ( (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) input CLKARDCLK, (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) input CLKBWRCLK, + (* invertible_pin = "IS_ENARDEN_INVERTED" *) input ENARDEN, + (* invertible_pin = "IS_ENBWREN_INVERTED" *) input ENBWREN, input REGCEAREGCE, input REGCEB, + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) input RSTRAMARSTRAM, + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) input RSTRAMB, + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) input RSTREGARSTREG, + (* invertible_pin = "IS_RSTREGB_INVERTED" *) input RSTREGB, input [13:0] ADDRARDADDR, @@ -132,16 +140,24 @@ endmodule module RAMB36E1 ( (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) input CLKARDCLK, (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) input CLKBWRCLK, + (* invertible_pin = "IS_ENARDEN_INVERTED" *) input ENARDEN, + (* invertible_pin = "IS_ENBWREN_INVERTED" *) input ENBWREN, input REGCEAREGCE, input REGCEB, + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) input RSTRAMARSTRAM, + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) input RSTRAMB, + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) input RSTREGARSTREG, + (* invertible_pin = "IS_RSTREGB_INVERTED" *) input RSTREGB, input [15:0] ADDRARDADDR, -- cgit v1.2.3