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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-15 23:01:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-15 23:01:40 -0700 |
| commit | 29a8d4745eb4ecd2947694d02f51c9333bf3ac21 (patch) | |
| tree | dd48a298f27bac04a189e8cf6acb261b845724c0 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 06f8f2654abdef8684bfe4f373ac42cb8c62ee2a (diff) | |
| download | yosys-29a8d4745eb4ecd2947694d02f51c9333bf3ac21.tar.gz yosys-29a8d4745eb4ecd2947694d02f51c9333bf3ac21.tar.bz2 yosys-29a8d4745eb4ecd2947694d02f51c9333bf3ac21.zip | |
Cleanup synth_xilinx
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 443ac4eed..763732fe5 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -110,6 +110,7 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); + log(" simplemap t:$dff*\n"); log(" shregmap -tech xilinx\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v +/xilinx/ff_map.v\n"); log(" opt -fast\n"); @@ -257,8 +258,6 @@ struct SynthXilinxPass : public Pass Pass::call(design, "simplemap t:$dff*"); Pass::call(design, "shregmap -tech xilinx"); - Pass::call(design, "techmap -map +/xilinx/cells_map.v t:$__SHREG_"); - Pass::call(design, "opt -fast"); if (vpr) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); |