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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-15 19:13:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-15 19:13:40 -0700 |
| commit | 06f8f2654abdef8684bfe4f373ac42cb8c62ee2a (patch) | |
| tree | 125e188a872f3ad5fdcda06d839735c9cfcc2007 /techlibs/xilinx/synth_xilinx.cc | |
| parent | e7ef7fa443c0b7c7ec9e4bbb15893053aed8c3ce (diff) | |
| download | yosys-06f8f2654abdef8684bfe4f373ac42cb8c62ee2a.tar.gz yosys-06f8f2654abdef8684bfe4f373ac42cb8c62ee2a.tar.bz2 yosys-06f8f2654abdef8684bfe4f373ac42cb8c62ee2a.zip | |
Working
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f2c3833a4..443ac4eed 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -110,9 +110,8 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); - log(" shregmap -init -params -enpol any_or_none\n"); - log(" techmap -map +/xilinx/ff_map.v\n"); + log(" shregmap -tech xilinx\n"); + log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); @@ -256,14 +255,17 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); + Pass::call(design, "simplemap t:$dff*"); + Pass::call(design, "shregmap -tech xilinx"); + Pass::call(design, "techmap -map +/xilinx/cells_map.v t:$__SHREG_"); + Pass::call(design, "opt -fast"); + if (vpr) { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); } else { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); } - Pass::call(design, "shregmap -init -params -enpol any_or_none"); - Pass::call(design, "techmap -map +/xilinx/ff_map.v"); Pass::call(design, "opt -fast"); } |