diff options
| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-09-21 15:46:43 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-09-21 15:46:43 +0200 |
| commit | 1ecf6aee9b331efebeca1bd95a3d5125abf8da50 (patch) | |
| tree | 279f98b936b6c739dce2cd0371de6307f3637550 /techlibs/sf2 | |
| parent | a217450524e21222d8d32bd448f1ea2291685258 (diff) | |
| download | yosys-1ecf6aee9b331efebeca1bd95a3d5125abf8da50.tar.gz yosys-1ecf6aee9b331efebeca1bd95a3d5125abf8da50.tar.bz2 yosys-1ecf6aee9b331efebeca1bd95a3d5125abf8da50.zip | |
Test fixes for latest iverilog
Diffstat (limited to 'techlibs/sf2')
| -rw-r--r-- | techlibs/sf2/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v index 02335404b..b5438e44c 100644 --- a/techlibs/sf2/cells_sim.v +++ b/techlibs/sf2/cells_sim.v @@ -162,7 +162,7 @@ module ARI1 ( wire F1 = INIT[8 + Fsel]; wire Yout = A ? F1 : F0; assign Y = Yout; - wire S = FCI ^ Yout; + assign S = FCI ^ Yout; wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17]; wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0); assign FCO = P ? FCI : G; |