Test fixes for latest iverilog

2 files changed, 2 insertions, 3 deletions

diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v
index 6c87adb94..fc15e0966 100644
--- a/techlibs/achronix/speedster22i/cells_sim.v
+++ b/techlibs/achronix/speedster22i/cells_sim.v
@@ -68,9 +68,8 @@ end
 assign dout = combout_rt & 1'b1;
 endmodule
 
-module DFF (output q,
+module DFF (output reg q,
             input  d, ck);
-   reg             q;
    always @(posedge ck)
      q <= d;
 
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index 02335404b..b5438e44c 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -162,7 +162,7 @@ module ARI1 (
 	wire F1 = INIT[8 + Fsel];
 	wire Yout = A ? F1 : F0;
 	assign Y = Yout;
-	wire S = FCI ^ Yout;
+	assign S = FCI ^ Yout;
 	wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];
 	wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);
 	assign FCO = P ? FCI : G;