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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-04-16 12:24:04 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-05-07 21:03:13 +0200 |
| commit | 5b779f7f4ef0bf2c4ad3a412da24fad30b078626 (patch) | |
| tree | cb0fcd56575efe8a846fbd6a2888aee80998f644 /techlibs/intel_alm/synth_intel_alm.cc | |
| parent | 06104249406972de01d0360df63a32cafcdf2ec5 (diff) | |
| download | yosys-5b779f7f4ef0bf2c4ad3a412da24fad30b078626.tar.gz yosys-5b779f7f4ef0bf2c4ad3a412da24fad30b078626.tar.bz2 yosys-5b779f7f4ef0bf2c4ad3a412da24fad30b078626.zip | |
intel_alm: direct LUTRAM cell instantiation
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
Diffstat (limited to 'techlibs/intel_alm/synth_intel_alm.cc')
| -rw-r--r-- | techlibs/intel_alm/synth_intel_alm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 200b0cdd1..bf9e746b8 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -164,6 +164,7 @@ struct SynthIntelALMPass : public ScriptPass { run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str())); + run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str())); // Misc and common cells run("read_verilog -lib +/intel/common/altpll_bb.v"); @@ -190,7 +191,6 @@ struct SynthIntelALMPass : public ScriptPass { if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V / Cyclone 10GX)"); - run("techmap -map +/intel_alm/common/lutram_mlab_map.v", "(for Cyclone V / Cyclone 10GX)"); } if (check_label("map_ffram")) { |