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| author | Clifford Wolf <clifford@clifford.at> | 2017-11-18 09:56:36 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-11-18 09:56:36 +0100 |
| commit | c01df04e32f7913622f40ced56fcb523ac96d35f (patch) | |
| tree | 87bb6d6a666a4246aa90bae9838b82ba62c41574 /techlibs/intel/synth_intel.cc | |
| parent | 234726c65537cf665681bf9af5bda6d57a90df23 (diff) | |
| parent | acee813a5c0d5517ea4123945e4971ddd2e5f3a4 (diff) | |
| download | yosys-c01df04e32f7913622f40ced56fcb523ac96d35f.tar.gz yosys-c01df04e32f7913622f40ced56fcb523ac96d35f.tar.bz2 yosys-c01df04e32f7913622f40ced56fcb523ac96d35f.zip | |
Merge pull request #453 from dh73/master
Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
Diffstat (limited to 'techlibs/intel/synth_intel.cc')
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 9e4b33601..9b3e92b14 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -127,7 +127,7 @@ struct SynthIntelPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive") + if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive" && family_opt != "cyclone10") log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); log_header(design, "Executing SYNTH_INTEL pass.\n"); @@ -148,6 +148,8 @@ struct SynthIntelPass : public ScriptPass { run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v"); else if(check_label("family") && family_opt=="cyclonev") run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v"); + else if(check_label("family") && family_opt=="cyclone10") + run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v"); else if(check_label("family") && family_opt=="cycloneiv") run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v"); else @@ -211,6 +213,8 @@ struct SynthIntelPass : public ScriptPass { run("techmap -map +/intel/a10gx/cells_map.v"); else if(family_opt=="cyclonev") run("techmap -map +/intel/cyclonev/cells_map.v"); + else if(family_opt=="cyclone10") + run("techmap -map +/intel/cyclone10/cells_map.v"); else if(family_opt=="cycloneiv") run("techmap -map +/intel/cycloneiv/cells_map.v"); else |