iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fitting help messages to 80 character width	KrystalDelusion	2022-08-24	1	-6/+7
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	Blackbox all whiteboxes after synthesis	gatecat	2021-03-17	1	-0/+1
*	synth_intel: Remove incomplete Arria 10 GX support.	Marcelina Kościelnicka	2020-08-21	1	-7/+3
*	intel: move Cyclone V support to intel_alm	Dan Ravensloft	2020-08-20	1	-4/+7
*	Replace opt_rmdff with opt_dff.	Marcelina Kościelnicka	2020-08-07	1	-2/+0
*	intel: Use dfflegalize.	Marcelina Kościelnicka	2020-07-13	1	-1/+5
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-4/+4
*	Get rid of dffsr2dff.	Marcelina Kościelnicka	2020-04-15	1	-1/+0
*	Add log_experimental() and experimental() API and "yosys -x"	Claire Wolf	2020-01-27	1	-1/+1
*	Merge pull request #1604 from whitequark/unify-ram-naming	whitequark	2020-01-02	1	-5/+5
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\| *	Harmonize BRAM/LUTRAM descriptions across all of Yosys.	whitequark	2020-01-01	1	-5/+5
* \|	Update doc that "-retime" calls abc with "-dff -D 1"	Eddie Hung	2019-12-30	1	-1/+1
* \|	Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""	Eddie Hung	2019-12-30	1	-1/+1
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*	synth_intel: a10gx -> arria10gx	Dan Ravensloft	2019-12-10	1	-3/+3
*	synth_intel: cyclone10 -> cyclone10lp	Dan Ravensloft	2019-12-10	1	-3/+3
*	Merge branch 'ZirconiumX-synth_intel_m9k'	Clifford Wolf	2019-07-25	1	-3/+9
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\| *	intel: Map M9K BRAM only on families that have it	Dan Ravensloft	2019-07-23	1	-3/+10
* \|	intel: Make -noiopads the default	Dan Ravensloft	2019-07-24	1	-8/+8
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*	Merge pull request #1208 from ZirconiumX/intel_cleanups	David Shah	2019-07-18	1	-29/+14
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\| *	synth_intel: Use stringf	Dan Ravensloft	2019-07-18	1	-7/+2
\| *	synth_intel: s/not family/no family/	Dan Ravensloft	2019-07-18	1	-2/+2
\| *	intel_synth: Fix help message	Ben Widawsky	2019-07-18	1	-1/+1
\| *	intel_synth: Small code cleanup to remove if ladder	Ben Widawsky	2019-07-18	1	-28/+10
\| *	intel_synth: Make family explicit and match	Ben Widawsky	2019-07-18	1	-2/+6
\| *	intel_synth: Minor code cleanups	Ben Widawsky	2019-07-18	1	-2/+6
* \|	synth_intel: rename for consistency with #1184	Dan Ravensloft	2019-07-18	1	-4/+4
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*	synth_intel: Warn about untested Quartus backend	Dan Ravensloft	2019-07-07	1	-0/+3
*	Fix formatting for synth_intel.cc	Ben Widawsky	2019-05-09	1	-222/+211
*	Unify usage of noflatten among architectures	Miodrag Milanovic	2019-01-04	1	-2/+2
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-6/+6
*	Add "synth_intel --noiopads"	Clifford Wolf	2018-04-30	1	-2/+11
*	Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val...	c60k28	2018-03-31	1	-4/+23
*	Add "dffinit -highlow" and fix synth_intel	Clifford Wolf	2018-01-09	1	-1/+1
*	Initial Cyclone 10 support	dh73	2017-11-08	1	-1/+5
*	Clean whitespace and permissions in techlibs/intel	Larry Doolittle	2017-10-05	1	-3/+3
*	Rename "write_verilog -nobasenradix" to "write_verilog -decimal"	Clifford Wolf	2017-10-03	1	-4/+1
*	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...	dh73	2017-10-01	1	-0/+241