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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-14 13:43:34 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 5ff60d2057992bdc9f0ff04eee78d7bf6be0ee44 (patch) | |
| tree | 0f5a602a3c667738b393453b21fd43fa4a0dad76 /techlibs/intel/synth_intel.cc | |
| parent | 683c5ce9409b578df518df829b76777ab69cf87b (diff) | |
| download | yosys-5ff60d2057992bdc9f0ff04eee78d7bf6be0ee44.tar.gz yosys-5ff60d2057992bdc9f0ff04eee78d7bf6be0ee44.tar.bz2 yosys-5ff60d2057992bdc9f0ff04eee78d7bf6be0ee44.zip | |
write_xaiger: add comment about arrival times of flop outputs
Diffstat (limited to 'techlibs/intel/synth_intel.cc')
0 files changed, 0 insertions, 0 deletions