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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-23 10:33:32 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-23 10:33:32 +0200 |
| commit | 34195f281fc4829f58c3dfc9c7944691044186e0 (patch) | |
| tree | efedfdaeb51623bede5949f3b5d2727d6f911911 /techlibs/greenpak4 | |
| parent | f85cfa56667e32ff9e165f9d957d05bde25342c0 (diff) | |
| parent | 0cbe70eaa40056a9d41070652282694cd7285b1a (diff) | |
| download | yosys-34195f281fc4829f58c3dfc9c7944691044186e0.tar.gz yosys-34195f281fc4829f58c3dfc9c7944691044186e0.tar.bz2 yosys-34195f281fc4829f58c3dfc9c7944691044186e0.zip | |
Merge https://github.com/azonenberg/yosys
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 554e2e13f..706e955b6 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -235,7 +235,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); reg[15:0] shreg = 0; - always @(posedge clk, negedge RSTN) begin + always @(posedge clk, negedge nRST) begin if(!nRST) shreg = 0; @@ -263,6 +263,12 @@ module GP_VDD(output OUT); assign OUT = 1; endmodule +module GP_VREF(input VIN, output reg VOUT); + parameter VIN_DIV = 1; + parameter VREF = 0; + //cannot simulate mixed signal IP +endmodule + module GP_VSS(output OUT); assign OUT = 0; endmodule |