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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:08:19 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:08:19 -0700 |
| commit | 0cbe70eaa40056a9d41070652282694cd7285b1a (patch) | |
| tree | ca0ac83098568aed8880e82e5529eda4140e9d51 /techlibs/greenpak4 | |
| parent | ab11f2aa701f4ff7a8df98d2a4158ea1f661a205 (diff) | |
| download | yosys-0cbe70eaa40056a9d41070652282694cd7285b1a.tar.gz yosys-0cbe70eaa40056a9d41070652282694cd7285b1a.tar.bz2 yosys-0cbe70eaa40056a9d41070652282694cd7285b1a.zip | |
Fixed typo
Diffstat (limited to 'techlibs/greenpak4')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 40d79aeae..706e955b6 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -235,7 +235,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); reg[15:0] shreg = 0; - always @(posedge clk, negedge RSTN) begin + always @(posedge clk, negedge nRST) begin if(!nRST) shreg = 0; |