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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-18 12:00:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-18 12:00:37 +0200 |
| commit | 745d56149d276f52146e302d59f74ede8d1875ba (patch) | |
| tree | d4e44c010631a538eef8f8cf95312edd89bd2ece /techlibs/greenpak4/cells_map.v | |
| parent | 452d4bf741cd46176c1dfbd232dd560e436b9f15 (diff) | |
| download | yosys-745d56149d276f52146e302d59f74ede8d1875ba.tar.gz yosys-745d56149d276f52146e302d59f74ede8d1875ba.tar.bz2 yosys-745d56149d276f52146e302d59f74ede8d1875ba.zip | |
Renamed GreenPAK4 cells, improved GP4 DFF mapping
Diffstat (limited to 'techlibs/greenpak4/cells_map.v')
| -rw-r--r-- | techlibs/greenpak4/cells_map.v | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v index 976687434..667d853da 100644 --- a/techlibs/greenpak4/cells_map.v +++ b/techlibs/greenpak4/cells_map.v @@ -1,5 +1,5 @@ module \$_DFF_P_ (input D, C, output Q); - DFF _TECHMAP_REPLACE_ ( + GP_DFF _TECHMAP_REPLACE_ ( .D(D), .Q(Q), .CLK(C), @@ -8,6 +8,16 @@ module \$_DFF_P_ (input D, C, output Q); ); endmodule +module \$_DFFSR_PNN_ (input C, S, R, D, output Q); + GP_DFF _TECHMAP_REPLACE_ ( + .D(D), + .Q(Q), + .CLK(C), + .nRSTZ(R), + .nSETZ(S) + ); +endmodule + module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; @@ -17,19 +27,19 @@ module \$lut (A, Y); generate if (WIDTH == 1) begin - LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y), + GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y), .IN0(A[0]), .IN1(1'b0)); end else if (WIDTH == 2) begin - LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y), + GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y), .IN0(A[0]), .IN1(A[1])); end else if (WIDTH == 3) begin - LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y), + GP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y), .IN0(A[0]), .IN1(A[1]), .IN2(A[2])); end else if (WIDTH == 4) begin - LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y), + GP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y), .IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3])); end else begin wire _TECHMAP_FAIL_ = 1; |