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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-09-21 18:01:31 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-21 18:01:31 +0200 |
| commit | 55801852289a17fd6e47a94a2d3333a206b9ee88 (patch) | |
| tree | 8d8b7fd94570a462f3c2c92a088b90b7df0c8f77 /techlibs/achronix | |
| parent | b2eb331b83072ec13377c8dc701e3dcf555255c1 (diff) | |
| parent | 1ecf6aee9b331efebeca1bd95a3d5125abf8da50 (diff) | |
| download | yosys-55801852289a17fd6e47a94a2d3333a206b9ee88.tar.gz yosys-55801852289a17fd6e47a94a2d3333a206b9ee88.tar.bz2 yosys-55801852289a17fd6e47a94a2d3333a206b9ee88.zip | |
Merge pull request #3488 from YosysHQ/micko/test_fix
Test fixes for latest iverilog
Diffstat (limited to 'techlibs/achronix')
| -rw-r--r-- | techlibs/achronix/speedster22i/cells_sim.v | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v index 6c87adb94..fc15e0966 100644 --- a/techlibs/achronix/speedster22i/cells_sim.v +++ b/techlibs/achronix/speedster22i/cells_sim.v @@ -68,9 +68,8 @@ end assign dout = combout_rt & 1'b1; endmodule -module DFF (output q, +module DFF (output reg q, input d, ck); - reg q; always @(posedge ck) q <= d; |