From 1ecf6aee9b331efebeca1bd95a3d5125abf8da50 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 21 Sep 2022 15:46:43 +0200 Subject: Test fixes for latest iverilog --- techlibs/achronix/speedster22i/cells_sim.v | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'techlibs/achronix') diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v index 6c87adb94..fc15e0966 100644 --- a/techlibs/achronix/speedster22i/cells_sim.v +++ b/techlibs/achronix/speedster22i/cells_sim.v @@ -68,9 +68,8 @@ end assign dout = combout_rt & 1'b1; endmodule -module DFF (output q, +module DFF (output reg q, input d, ck); - reg q; always @(posedge ck) q <= d; -- cgit v1.2.3