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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:23:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:23:22 -0700 |
| commit | fd3b033903bf005c4308923ccb34ab269d55dd3e (patch) | |
| tree | bdb846f228a6517612fab5b7f19a642c91fd093d /passes | |
| parent | 25e0f0c3765060b7ce25a0c58bc926b90dba304d (diff) | |
| parent | 3ec28ec53a4350d041cd24a4fa9b03e985d20d95 (diff) | |
| download | yosys-fd3b033903bf005c4308923ccb34ab269d55dd3e.tar.gz yosys-fd3b033903bf005c4308923ccb34ab269d55dd3e.tar.bz2 yosys-fd3b033903bf005c4308923ccb34ab269d55dd3e.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_expr.cc | 4 | ||||
| -rw-r--r-- | passes/techmap/alumacc.cc | 19 |
2 files changed, 19 insertions, 4 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 00d7d6063..6cf66fb95 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -953,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (b.is_fully_const()) { + if (b.is_fully_undef()) { + RTLIL::SigSpec input = b; + ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y)))); + } else if (b.as_bool() == (cell->type == ID($eq))) { RTLIL::SigSpec input = b; ACTION_DO(ID::Y, cell->getPort(ID::A)); diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 5b168d524..034731b87 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -48,14 +48,25 @@ struct AlumaccWorker RTLIL::SigSpec cached_cf, cached_of, cached_sf; RTLIL::SigSpec get_lt() { - if (GetSize(cached_lt) == 0) - cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf(); + if (GetSize(cached_lt) == 0) { + if (is_signed) { + get_of(); + get_sf(); + cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf); + } + else + cached_lt = get_cf(); + } return cached_lt; } RTLIL::SigSpec get_gt() { - if (GetSize(cached_gt) == 0) - cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute()); + if (GetSize(cached_gt) == 0) { + get_lt(); + get_eq(); + SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq); + cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute()); + } return cached_gt; } |