From 4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Sep 2019 11:45:02 -0700 Subject: SigSet to use stable compare class --- passes/cmds/scc.cc | 2 +- passes/opt/opt_reduce.cc | 4 ++-- passes/opt/opt_rmdff.cc | 2 +- passes/sat/sat.cc | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 99f4fbae8..0a4f9e98d 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -116,7 +116,7 @@ struct SccWorker } SigPool selectedSignals; - SigSet sigToNextCells; + SigSet> sigToNextCells; for (auto &it : module->wires_) if (design->selected(module, it.second)) diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 6a8d8cabd..9850775af 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -37,7 +37,7 @@ struct OptReduceWorker int total_count; bool did_something; - void opt_reduce(pool &cells, SigSet &drivers, RTLIL::Cell *cell) + void opt_reduce(pool &cells, SigSet> &drivers, RTLIL::Cell *cell) { if (cells.count(cell) == 0) return; @@ -289,7 +289,7 @@ struct OptReduceWorker const IdString type_list[] = { ID($reduce_or), ID($reduce_and) }; for (auto type : type_list) { - SigSet drivers; + SigSet> drivers; pool cells; for (auto &cell_it : module->cells_) { diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 0bf74098a..8d4b6b14b 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -29,7 +29,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN SigMap assign_map, dff_init_map; -SigSet mux_drivers; +SigSet> mux_drivers; dict bit2driver; dict> init_attributes; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 430bba1e8..097fc5a2e 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -61,7 +61,7 @@ struct SatHelper // model variables std::vector shows; SigPool show_signal_pool; - SigSet show_drivers; + SigSet> show_drivers; int max_timestep, timeout; bool gotTimeout; -- cgit v1.2.3 From a67d63714be52e4a4f789c2a82b6283748db8902 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 13 Sep 2019 13:39:39 +0200 Subject: Fix handling of z_digit "?" and fix optimization of cmp with "z" Signed-off-by: Clifford Wolf --- passes/opt/opt_expr.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'passes') diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 00d7d6063..6cf66fb95 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -953,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (b.is_fully_const()) { + if (b.is_fully_undef()) { + RTLIL::SigSpec input = b; + ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y)))); + } else if (b.as_bool() == (cell->type == ID($eq))) { RTLIL::SigSpec input = b; ACTION_DO(ID::Y, cell->getPort(ID::A)); -- cgit v1.2.3 From 95e80809a5801743fabb2836fa25f3c3732a9a24 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 09:49:15 -0700 Subject: Revert "SigSet to use stable compare class" This reverts commit 4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11. --- passes/cmds/scc.cc | 2 +- passes/opt/opt_reduce.cc | 4 ++-- passes/opt/opt_rmdff.cc | 2 +- passes/sat/sat.cc | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'passes') diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 0a4f9e98d..99f4fbae8 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -116,7 +116,7 @@ struct SccWorker } SigPool selectedSignals; - SigSet> sigToNextCells; + SigSet sigToNextCells; for (auto &it : module->wires_) if (design->selected(module, it.second)) diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 9850775af..6a8d8cabd 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -37,7 +37,7 @@ struct OptReduceWorker int total_count; bool did_something; - void opt_reduce(pool &cells, SigSet> &drivers, RTLIL::Cell *cell) + void opt_reduce(pool &cells, SigSet &drivers, RTLIL::Cell *cell) { if (cells.count(cell) == 0) return; @@ -289,7 +289,7 @@ struct OptReduceWorker const IdString type_list[] = { ID($reduce_or), ID($reduce_and) }; for (auto type : type_list) { - SigSet> drivers; + SigSet drivers; pool cells; for (auto &cell_it : module->cells_) { diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 8d4b6b14b..0bf74098a 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -29,7 +29,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN SigMap assign_map, dff_init_map; -SigSet> mux_drivers; +SigSet mux_drivers; dict bit2driver; dict> init_attributes; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 097fc5a2e..430bba1e8 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -61,7 +61,7 @@ struct SatHelper // model variables std::vector shows; SigPool show_signal_pool; - SigSet> show_drivers; + SigSet show_drivers; int max_timestep, timeout; bool gotTimeout; -- cgit v1.2.3 From 9a73adde5016346078f336c296c2a54f44210246 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Sep 2019 16:18:05 -0700 Subject: Explicitly order function arguments --- passes/techmap/alumacc.cc | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'passes') diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 5b168d524..034731b87 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -48,14 +48,25 @@ struct AlumaccWorker RTLIL::SigSpec cached_cf, cached_of, cached_sf; RTLIL::SigSpec get_lt() { - if (GetSize(cached_lt) == 0) - cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf(); + if (GetSize(cached_lt) == 0) { + if (is_signed) { + get_of(); + get_sf(); + cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf); + } + else + cached_lt = get_cf(); + } return cached_lt; } RTLIL::SigSpec get_gt() { - if (GetSize(cached_gt) == 0) - cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute()); + if (GetSize(cached_gt) == 0) { + get_lt(); + get_eq(); + SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq); + cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute()); + } return cached_gt; } -- cgit v1.2.3