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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-11-25 13:02:11 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-11-25 13:02:11 +0100 |
| commit | b0be19c1267b794fb08bc7a8c7174ebbfb9fce7d (patch) | |
| tree | 118315aa9506eb25ed79505cbdc3acf05cf2ac53 /passes | |
| parent | fc2f622a27dbc604a4acce68bea8c20b208c1742 (diff) | |
| download | yosys-b0be19c1267b794fb08bc7a8c7174ebbfb9fce7d.tar.gz yosys-b0be19c1267b794fb08bc7a8c7174ebbfb9fce7d.tar.bz2 yosys-b0be19c1267b794fb08bc7a8c7174ebbfb9fce7d.zip | |
Support importing verilog configurations using Verific
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index eea6abb04..bf0137503 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -960,7 +960,7 @@ struct HierarchyPass : public Pass { if (top_mod == nullptr && !load_top_mod.empty()) { #ifdef YOSYS_ENABLE_VERIFIC if (verific_import_pending) { - verific_import(design, parameters, load_top_mod); + load_top_mod = verific_import(design, parameters, load_top_mod); top_mod = design->module(RTLIL::escape_id(load_top_mod)); } #endif |