From b0be19c1267b794fb08bc7a8c7174ebbfb9fce7d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 25 Nov 2022 13:02:11 +0100
Subject: Support importing verilog configurations using Verific

---
 passes/hierarchy/hierarchy.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'passes')

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index eea6abb04..bf0137503 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -960,7 +960,7 @@ struct HierarchyPass : public Pass {
 		if (top_mod == nullptr && !load_top_mod.empty()) {
 #ifdef YOSYS_ENABLE_VERIFIC
 			if (verific_import_pending) {
-				verific_import(design, parameters, load_top_mod);
+				load_top_mod = verific_import(design, parameters, load_top_mod);
 				top_mod = design->module(RTLIL::escape_id(load_top_mod));
 			}
 #endif
-- 
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