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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 22:54:56 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-01 08:33:32 -0800 |
| commit | ac808c5e2aa0fbcfb5b56160131fcc61ba13da05 (patch) | |
| tree | a4b57b2f1901837de9551eb47a48ff771471400c /passes | |
| parent | 44d9fb0e7cee7d8986ed037429e3c9fdd1b29ba1 (diff) | |
| download | yosys-ac808c5e2aa0fbcfb5b56160131fcc61ba13da05.tar.gz yosys-ac808c5e2aa0fbcfb5b56160131fcc61ba13da05.tar.bz2 yosys-ac808c5e2aa0fbcfb5b56160131fcc61ba13da05.zip | |
attributes.count() -> get_bool_attribute()
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 3c53a5223..d6c8260b2 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -533,7 +533,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip } RTLIL::Module* box_module = design->module(mapped_cell->type); - auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop"); + auto abc9_flop = box_module && box_module->get_bool_attribute("\\abc9_flop"); for (auto &conn : mapped_cell->connections()) { RTLIL::SigSpec newsig; for (auto c : conn.second.chunks()) { @@ -988,7 +988,7 @@ struct Abc9Pass : public Pass { for (auto cell : all_cells) { auto inst_module = design->module(cell->type); - if (!inst_module || !inst_module->attributes.count("\\abc9_flop") + if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop") || cell->get_bool_attribute("\\abc9_keep")) continue; |