From ac808c5e2aa0fbcfb5b56160131fcc61ba13da05 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 22:54:56 -0800 Subject: attributes.count() -> get_bool_attribute() --- passes/techmap/abc9.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'passes') diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 3c53a5223..d6c8260b2 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -533,7 +533,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip } RTLIL::Module* box_module = design->module(mapped_cell->type); - auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop"); + auto abc9_flop = box_module && box_module->get_bool_attribute("\\abc9_flop"); for (auto &conn : mapped_cell->connections()) { RTLIL::SigSpec newsig; for (auto c : conn.second.chunks()) { @@ -988,7 +988,7 @@ struct Abc9Pass : public Pass { for (auto cell : all_cells) { auto inst_module = design->module(cell->type); - if (!inst_module || !inst_module->attributes.count("\\abc9_flop") + if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop") || cell->get_bool_attribute("\\abc9_keep")) continue; -- cgit v1.2.3