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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-10 07:24:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-10 07:24:26 +0200 |
| commit | 56d48227195139f9b85c9f868a192c116266dac4 (patch) | |
| tree | 2f0b3bf67ccc8c88c2dea065669901ba1898b1e6 /passes/techmap | |
| parent | 85287295b27dc3d51d2958dccb4f9098984b794a (diff) | |
| download | yosys-56d48227195139f9b85c9f868a192c116266dac4.tar.gz yosys-56d48227195139f9b85c9f868a192c116266dac4.tar.bz2 yosys-56d48227195139f9b85c9f868a192c116266dac4.zip | |
Renamed "aig" to "aigmap"
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/Makefile.inc | 2 | ||||
| -rw-r--r-- | passes/techmap/aigmap.cc (renamed from passes/techmap/aig.cc) | 10 |
2 files changed, 6 insertions, 6 deletions
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 3cbee5b85..e39d5c5c2 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -18,7 +18,7 @@ OBJS += passes/techmap/dff2dffe.o OBJS += passes/techmap/dffinit.o OBJS += passes/techmap/pmuxtree.o OBJS += passes/techmap/muxcover.o -OBJS += passes/techmap/aig.o +OBJS += passes/techmap/aigmap.o endif GENFILES += passes/techmap/techmap.inc diff --git a/passes/techmap/aig.cc b/passes/techmap/aigmap.cc index 3bd078537..9f552e3e5 100644 --- a/passes/techmap/aig.cc +++ b/passes/techmap/aigmap.cc @@ -23,12 +23,12 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct AigPass : public Pass { - AigPass() : Pass("aig", "convert logic to and-inverter circuit") { } +struct AigmapPass : public Pass { + AigmapPass() : Pass("aigmap", "map logic to and-inverter-graph circuit") { } virtual void help() { log("\n"); - log(" aig [options] [selection]\n"); + log(" aigmap [options] [selection]\n"); log("\n"); log("Replace all logic cells with circuits made of only $_AND_ and\n"); log("$_NOT_ cells.\n"); @@ -41,7 +41,7 @@ struct AigPass : public Pass { { bool nand_mode = false; - log_header("Executing AIG pass (converting logic to AIG).\n"); + log_header("Executing AIGMAP pass (map logic to AIG).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -144,6 +144,6 @@ struct AigPass : public Pass { module->remove(cell); } } -} AigPass; +} AigmapPass; PRIVATE_NAMESPACE_END |