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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-10 07:16:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-10 07:16:30 +0200 |
| commit | 85287295b27dc3d51d2958dccb4f9098984b794a (patch) | |
| tree | 03d1517947ed1dc553e3cb1a765b785dc0014645 /passes/techmap | |
| parent | 66f9ee412ae94fa305660bdc33fa0c00fedd5500 (diff) | |
| download | yosys-85287295b27dc3d51d2958dccb4f9098984b794a.tar.gz yosys-85287295b27dc3d51d2958dccb4f9098984b794a.tar.bz2 yosys-85287295b27dc3d51d2958dccb4f9098984b794a.zip | |
Fixed cellaigs port extending
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/aig.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/passes/techmap/aig.cc b/passes/techmap/aig.cc index 0c0f0b130..3bd078537 100644 --- a/passes/techmap/aig.cc +++ b/passes/techmap/aig.cc @@ -90,12 +90,13 @@ struct AigPass : public Pass { bit = cell->getPort(node.portname)[node.portbit]; } else if (node.left_parent < 0 && node.right_parent < 0) { bit = node.inverter ? State::S0 : State::S1; + goto skip_inverter; } else { SigBit A = sigs.at(node.left_parent); SigBit B = sigs.at(node.right_parent); if (nand_mode && node.inverter) { bit = module->NandGate(NEW_ID, A, B); - goto nand_inverter; + goto skip_inverter; } else { pair<int, int> key(node.left_parent, node.right_parent); if (and_cache.count(key)) @@ -108,7 +109,7 @@ struct AigPass : public Pass { if (node.inverter) bit = module->NotGate(NEW_ID, bit); - nand_inverter: + skip_inverter: for (auto &op : node.outports) module->connect(cell->getPort(op.first)[op.second], bit); |