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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 14:27:29 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 14:27:29 -0800 |
| commit | 4656f202c6f05d126c1acc79fca675e467c80840 (patch) | |
| tree | b6c3fbb378cfb0191492260220289e7a3ae2502e /passes/techmap | |
| parent | 654247abe9078566f93960a135ce08b0cfc96442 (diff) | |
| download | yosys-4656f202c6f05d126c1acc79fca675e467c80840.tar.gz yosys-4656f202c6f05d126c1acc79fca675e467c80840.tar.bz2 yosys-4656f202c6f05d126c1acc79fca675e467c80840.zip | |
abc9_ops: -reintegrate to not trim box padding anymore
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 463941b0b..aa21ff283 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -562,15 +562,6 @@ void reintegrate(RTLIL::Module *module) c.wire = module->wires_.at(remap_name(c.wire->name)); newsig.append(c); } - - auto it = existing_cell->connections_.find(port_name); - if (it == existing_cell->connections_.end()) - continue; - if (GetSize(newsig) > GetSize(it->second)) - newsig = newsig.extract(0, GetSize(it->second)); - else - log_assert(GetSize(newsig) == GetSize(it->second)); - cell->setPort(port_name, newsig); if (w->port_input && !abc9_flop) |