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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 12:40:36 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 12:40:36 -0800 |
| commit | 654247abe9078566f93960a135ce08b0cfc96442 (patch) | |
| tree | 2a7f74011de10ebcc70f41db53e3c19b4536d8e4 /passes/techmap | |
| parent | 468386d67d902722562e9a0412a76fca79ec4fa2 (diff) | |
| download | yosys-654247abe9078566f93960a135ce08b0cfc96442.tar.gz yosys-654247abe9078566f93960a135ce08b0cfc96442.tar.bz2 yosys-654247abe9078566f93960a135ce08b0cfc96442.zip | |
abc9_ops/write_xaiger: update doc
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 405f3e267..463941b0b 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -739,6 +739,19 @@ struct Abc9OpsPass : public Pass { log(" '<module-name>$holes' module that contains the logic behaviour of ABC9\n"); log(" whiteboxes.\n"); log("\n"); + log(" -dff\n"); + log(" consider flop cells (those instantiating modules marked with (* abc9_flop *)\n"); + log(" during -prep_xaiger.\n"); + log("\n"); + log(" -prep_dff\n"); + log(" compute the clock domain and initial value of each flop in the design.\n"); + log(" process the '$holes' module to support clock-enable functionality.\n"); + log("\n"); + log(" -reintegrate\n"); + log(" for each selected module, re-intergrate the module '<module-name>$abc9'\n"); + log(" by first recovering ABC9 boxes, and then stitching in the remaining primary\n"); + log(" inputs and outputs.\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { |