diff options
| -rw-r--r-- | backends/btor/btor.cc | 4 | ||||
| -rw-r--r-- | backends/firrtl/firrtl.cc | 4 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 4 | ||||
| -rw-r--r-- | frontends/verific/verificsva.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_map.cc | 4 | ||||
| -rw-r--r-- | passes/memory/memory_collect.cc | 10 | ||||
| -rw-r--r-- | passes/memory/memory_map.cc | 2 | ||||
| -rw-r--r-- | passes/sat/eval.cc | 4 | ||||
| -rw-r--r-- | passes/sat/miter.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/simplemap.cc | 2 |
10 files changed, 19 insertions, 19 deletions
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 7bacce2af..7c054d655 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -616,8 +616,8 @@ struct BtorWorker if (initstate_nid < 0) { int sid = get_bv_sid(1); - int one_nid = get_sig_nid(Const(1, 1)); - int zero_nid = get_sig_nid(Const(0, 1)); + int one_nid = get_sig_nid(State::S1); + int zero_nid = get_sig_nid(State::S0); initstate_nid = next_nid++; btorf("%d state %d\n", initstate_nid, sid); btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid); diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 1c7a7351f..4758c6d4d 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -122,9 +122,9 @@ struct FirrtlWorker // Current (3/13/2019) conventions: // generate a constant 0 for clock and a constant 1 for enable if they are undefined. if (!clk.is_fully_def()) - this->clk = SigSpec(RTLIL::Const(0, 1)); + this->clk = SigSpec(State::S0); if (!ena.is_fully_def()) - this->ena = SigSpec(RTLIL::Const(1, 1)); + this->ena = SigSpec(State::S1); } string gen_read(const char * indent) { string addr_expr = make_expr(addr); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 9a797b535..6cb053f1d 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -380,9 +380,9 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, for (auto it = attributes.begin(); it != attributes.end(); ++it) { f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str()); f << stringf(" = "); - if (modattr && (it->second == Const(0, 1) || it->second == Const(0))) + if (modattr && (it->second == State::S0 || it->second == Const(0))) f << stringf(" 0 "); - else if (modattr && (it->second == Const(1, 1) || it->second == Const(1))) + else if (modattr && (it->second == State::S1 || it->second == Const(1))) f << stringf(" 1 "); else dump_const(f, it->second, -1, 0, false, as_comment); diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 8ea8372d3..909e9b4f1 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -357,7 +357,7 @@ struct SvaFsm for (int i = 0; i < GetSize(nodes); i++) { if (next_state_sig[i] != State::S0) { - clocking.addDff(NEW_ID, next_state_sig[i], state_wire[i], Const(0, 1)); + clocking.addDff(NEW_ID, next_state_sig[i], state_wire[i], State::S0); } else { module->connect(state_wire[i], State::S0); } diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 90c958912..80913fda8 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -133,7 +133,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const cases_vector.append(and_sig); break; case 0: - cases_vector.append(RTLIL::SigSpec(1, 1)); + cases_vector.append(State::S1); break; default: log_abort(); @@ -150,7 +150,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const } else if (cases_vector.size() == 1) { module->connect(RTLIL::SigSig(output, cases_vector)); } else { - module->connect(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); + module->connect(RTLIL::SigSig(output, State::S0)); } } diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 369fcc84e..6acbce62f 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -194,8 +194,8 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) log_assert(sig_wr_en.size() == wr_ports * memory->width); mem->parameters["\\WR_PORTS"] = Const(wr_ports); - mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : Const(0, 1); - mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : Const(0, 1); + mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0; + mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0; mem->setPort("\\WR_CLK", sig_wr_clk); mem->setPort("\\WR_ADDR", sig_wr_addr); @@ -209,9 +209,9 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) log_assert(sig_rd_data.size() == rd_ports * memory->width); mem->parameters["\\RD_PORTS"] = Const(rd_ports); - mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : Const(0, 1); - mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : Const(0, 1); - mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : Const(0, 1); + mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0; + mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0; + mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : State::S0; mem->setPort("\\RD_CLK", sig_rd_clk); mem->setPort("\\RD_ADDR", sig_rd_addr); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index a0b808e56..65bccb5ef 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -301,7 +301,7 @@ struct MemoryMapWorker RTLIL::Wire *w = w_seladdr; - if (wr_bit != RTLIL::SigSpec(1, 1)) + if (wr_bit != State::S1) { RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); c->parameters["\\A_SIGNED"] = RTLIL::Const(0); diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 008cd2dfa..e0bb439f4 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -47,8 +47,8 @@ struct BruteForceEquivChecker { if (inputs.size() < mod1_inputs.size()) { RTLIL::SigSpec inputs0 = inputs, inputs1 = inputs; - inputs0.append(RTLIL::Const(0, 1)); - inputs1.append(RTLIL::Const(1, 1)); + inputs0.append(State::S0); + inputs1.append(State::S1); run_checker(inputs0); run_checker(inputs1); return; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 1a886af70..e1da1a9e6 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -236,7 +236,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: if (flag_make_assert) { RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert"); assert_cell->setPort("\\A", all_conditions); - assert_cell->setPort("\\EN", RTLIL::SigSpec(1, 1)); + assert_cell->setPort("\\EN", State::S1); } RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger"); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 6c70ffd4f..2eaba1b09 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -185,7 +185,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell } if (sig.size() == 0) - sig = RTLIL::SigSpec(0, 1); + sig = State::S0; } void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) |