kernel: use more ID::*

9 files changed, 60 insertions, 60 deletions

diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc
index 3b432c461..b4adb1ab3 100644
--- a/passes/sat/assertpmux.cc
+++ b/passes/sat/assertpmux.cc
@@ -57,9 +57,9 @@ struct AssertpmuxWorker
 				int width = cell->getParam("\\WIDTH").as_int();
 				int numports = cell->type == "$mux" ? 2 : cell->getParam("\\S_WIDTH").as_int() + 1;
 
-				SigSpec sig_a = sigmap(cell->getPort("\\A"));
-				SigSpec sig_b = sigmap(cell->getPort("\\B"));
-				SigSpec sig_s = sigmap(cell->getPort("\\S"));
+				SigSpec sig_a = sigmap(cell->getPort(ID::A));
+				SigSpec sig_b = sigmap(cell->getPort(ID::B));
+				SigSpec sig_s = sigmap(cell->getPort(ID::S));
 
 				for (int i = 0; i < numports; i++) {
 					SigSpec bits = i == 0 ? sig_a : sig_b.extract(width*(i-1), width);
@@ -98,12 +98,12 @@ struct AssertpmuxWorker
 
 				if (muxport_actsignal.count(muxport) == 0) {
 					if (portidx == 0)
-						muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort("\\S"));
+						muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(ID::S));
 					else
-						muxport_actsignal[muxport] = cell->getPort("\\S")[portidx-1];
+						muxport_actsignal[muxport] = cell->getPort(ID::S)[portidx-1];
 				}
 
-				output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort("\\Y")[bitidx])));
+				output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx])));
 			}
 
 			output.sort_and_unify();
@@ -151,7 +151,7 @@ struct AssertpmuxWorker
 		int swidth = pmux->getParam("\\S_WIDTH").as_int();
 		int cntbits = ceil_log2(swidth+1);
 
-		SigSpec sel = pmux->getPort("\\S");
+		SigSpec sel = pmux->getPort(ID::S);
 		SigSpec cnt(State::S0, cntbits);
 
 		for (int i = 0; i < swidth; i++)
@@ -164,7 +164,7 @@ struct AssertpmuxWorker
 			assert_en.append(module->LogicNot(NEW_ID, module->Initstate(NEW_ID)));
 
 		if (!flag_always)
-			assert_en.append(get_activation(pmux->getPort("\\Y")));
+			assert_en.append(get_activation(pmux->getPort(ID::Y)));
 
 		if (GetSize(assert_en) == 0)
 			assert_en = State::S1;
@@ -174,8 +174,8 @@ struct AssertpmuxWorker
 
 		Cell *assert_cell = module->addAssert(NEW_ID, assert_a, assert_en);
 
-		if (pmux->attributes.count("\\src") != 0)
-			assert_cell->attributes["\\src"] = pmux->attributes.at("\\src");
+		if (pmux->attributes.count(ID::src) != 0)
+			assert_cell->attributes[ID::src] = pmux->attributes.at(ID::src);
 	}
 };
 
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index 24aba22f3..cc16a767c 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -336,7 +336,7 @@ struct Clk2fflogicPass : public Pass {
 						ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
 					{
 						SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
-						SigSpec setval = cell->getPort("\\S");
+						SigSpec setval = cell->getPort(ID::S);
 						SigSpec clrval = cell->getPort("\\R");
 
 						if (cell->type[9] != 'P')
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 8fb47f357..4f0ba44f6 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -562,8 +562,8 @@ struct ExposePass : public Pass {
 					c->parameters["\\A_SIGNED"] = 0;
 					c->parameters["\\A_WIDTH"] = 1;
 					c->parameters["\\Y_WIDTH"] = 1;
-					c->setPort("\\A", info.sig_clk);
-					c->setPort("\\Y", wire_c);
+					c->setPort(ID::A, info.sig_clk);
+					c->setPort(ID::Y, wire_c);
 				}
 
 				if (info.sig_arst != RTLIL::State::Sm)
@@ -578,8 +578,8 @@ struct ExposePass : public Pass {
 						c->parameters["\\A_SIGNED"] = 0;
 						c->parameters["\\A_WIDTH"] = 1;
 						c->parameters["\\Y_WIDTH"] = 1;
-						c->setPort("\\A", info.sig_arst);
-						c->setPort("\\Y", wire_r);
+						c->setPort(ID::A, info.sig_arst);
+						c->setPort(ID::Y, wire_r);
 					}
 
 					RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width);
diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc
index 00c098542..18eeb37b5 100644
--- a/passes/sat/fmcombine.cc
+++ b/passes/sat/fmcombine.cc
@@ -359,7 +359,7 @@ struct FmcombinePass : public Pass {
 
 		Cell *cell = module->addCell(combined_cell_name, worker.combined_type);
 		cell->attributes = gold_cell->attributes;
-		cell->add_strpool_attribute("\\src", gate_cell->get_strpool_attribute("\\src"));
+		cell->add_strpool_attribute(ID::src, gate_cell->get_strpool_attribute(ID::src));
 
 		log("Combining cells %s and %s in module %s into new cell %s.\n", log_id(gold_cell), log_id(gate_cell), log_id(module), log_id(cell));
 
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 54016e528..020e2a74c 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -635,8 +635,8 @@ struct FreduceWorker
 				batches.push_back(outputs);
 				bits_full_total += outputs.size();
 			}
-			if (inv_mode && cell->type == "$_NOT_")
-				inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\Y"))));
+			if (inv_mode && cell->type == ID($_NOT_))
+				inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort(ID::A)), sigmap(cell->getPort(ID::Y))));
 		}
 
 		int bits_count = 0;
@@ -732,8 +732,8 @@ struct FreduceWorker
 						inv_sig = module->addWire(NEW_ID);
 
 						RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_");
-						inv_cell->setPort("\\A", grp[0].bit);
-						inv_cell->setPort("\\Y", inv_sig);
+						inv_cell->setPort(ID::A, grp[0].bit);
+						inv_cell->setPort(ID::Y, inv_sig);
 					}
 
 					module->connect(RTLIL::SigSig(grp[i].bit, inv_sig));
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 742433935..f5bc251c2 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -155,9 +155,9 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 					eqx_cell->parameters["\\Y_WIDTH"] = 1;
 					eqx_cell->parameters["\\A_SIGNED"] = 0;
 					eqx_cell->parameters["\\B_SIGNED"] = 0;
-					eqx_cell->setPort("\\A", RTLIL::SigSpec(w_gold, i));
-					eqx_cell->setPort("\\B", RTLIL::State::Sx);
-					eqx_cell->setPort("\\Y", gold_x.extract(i, 1));
+					eqx_cell->setPort(ID::A, RTLIL::SigSpec(w_gold, i));
+					eqx_cell->setPort(ID::B, RTLIL::State::Sx);
+					eqx_cell->setPort(ID::Y, gold_x.extract(i, 1));
 				}
 
 				RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width);
@@ -169,9 +169,9 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 				or_gold_cell->parameters["\\Y_WIDTH"] = w_gold->width;
 				or_gold_cell->parameters["\\A_SIGNED"] = 0;
 				or_gold_cell->parameters["\\B_SIGNED"] = 0;
-				or_gold_cell->setPort("\\A", w_gold);
-				or_gold_cell->setPort("\\B", gold_x);
-				or_gold_cell->setPort("\\Y", gold_masked);
+				or_gold_cell->setPort(ID::A, w_gold);
+				or_gold_cell->setPort(ID::B, gold_x);
+				or_gold_cell->setPort(ID::Y, gold_masked);
 
 				RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
 				or_gate_cell->parameters["\\A_WIDTH"] = w_gate->width;
@@ -179,9 +179,9 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 				or_gate_cell->parameters["\\Y_WIDTH"] = w_gate->width;
 				or_gate_cell->parameters["\\A_SIGNED"] = 0;
 				or_gate_cell->parameters["\\B_SIGNED"] = 0;
-				or_gate_cell->setPort("\\A", w_gate);
-				or_gate_cell->setPort("\\B", gold_x);
-				or_gate_cell->setPort("\\Y", gate_masked);
+				or_gate_cell->setPort(ID::A, w_gate);
+				or_gate_cell->setPort(ID::B, gold_x);
+				or_gate_cell->setPort(ID::Y, gate_masked);
 
 				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
 				eq_cell->parameters["\\A_WIDTH"] = w_gold->width;
@@ -189,10 +189,10 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 				eq_cell->parameters["\\Y_WIDTH"] = 1;
 				eq_cell->parameters["\\A_SIGNED"] = 0;
 				eq_cell->parameters["\\B_SIGNED"] = 0;
-				eq_cell->setPort("\\A", gold_masked);
-				eq_cell->setPort("\\B", gate_masked);
-				eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
-				this_condition = eq_cell->getPort("\\Y");
+				eq_cell->setPort(ID::A, gold_masked);
+				eq_cell->setPort(ID::B, gate_masked);
+				eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
+				this_condition = eq_cell->getPort(ID::Y);
 			}
 			else
 			{
@@ -202,10 +202,10 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 				eq_cell->parameters["\\Y_WIDTH"] = 1;
 				eq_cell->parameters["\\A_SIGNED"] = 0;
 				eq_cell->parameters["\\B_SIGNED"] = 0;
-				eq_cell->setPort("\\A", w_gold);
-				eq_cell->setPort("\\B", w_gate);
-				eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
-				this_condition = eq_cell->getPort("\\Y");
+				eq_cell->setPort(ID::A, w_gold);
+				eq_cell->setPort(ID::B, w_gate);
+				eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
+				this_condition = eq_cell->getPort(ID::Y);
 			}
 
 			if (flag_make_outcmp)
@@ -224,14 +224,14 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 		reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
 		reduce_cell->parameters["\\Y_WIDTH"] = 1;
 		reduce_cell->parameters["\\A_SIGNED"] = 0;
-		reduce_cell->setPort("\\A", all_conditions);
-		reduce_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
-		all_conditions = reduce_cell->getPort("\\Y");
+		reduce_cell->setPort(ID::A, all_conditions);
+		reduce_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
+		all_conditions = reduce_cell->getPort(ID::Y);
 	}
 
 	if (flag_make_assert) {
 		RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert");
-		assert_cell->setPort("\\A", all_conditions);
+		assert_cell->setPort(ID::A, all_conditions);
 		assert_cell->setPort("\\EN", State::S1);
 	}
 
@@ -243,8 +243,8 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 	not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
 	not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
 	not_cell->parameters["\\A_SIGNED"] = 0;
-	not_cell->setPort("\\A", all_conditions);
-	not_cell->setPort("\\Y", w_trigger);
+	not_cell->setPort(ID::A, all_conditions);
+	not_cell->setPort(ID::Y, w_trigger);
 
 	miter_module->fixup_ports();
 
@@ -315,7 +315,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
 		if (!cell->type.in("$assert", "$assume"))
 			continue;
 
-		SigBit is_active = module->Nex(NEW_ID, cell->getPort("\\A"), State::S1);
+		SigBit is_active = module->Nex(NEW_ID, cell->getPort(ID::A), State::S1);
 		SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1);
 
 		if (cell->type == "$assert") {
diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index b53bbfeb2..af8ffca9e 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -439,7 +439,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 		dict<SigBit, int> bit_user_cnt;
 
 		for (auto wire : module->wires()) {
-			if (wire->name[0] == '\\' && wire->attributes.count("\\src"))
+			if (wire->name[0] == '\\' && wire->attributes.count(ID::src))
 				sigmap.add(wire);
 		}
 
@@ -489,12 +489,12 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 					entry.port = conn.first;
 					entry.portbit = i;
 
-					for (auto &s : cell->get_strpool_attribute("\\src"))
+					for (auto &s : cell->get_strpool_attribute(ID::src))
 						entry.src.insert(s);
 
 					SigBit bit = sigmap(conn.second[i]);
 					if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
-						for (auto &s : bit.wire->get_strpool_attribute("\\src"))
+						for (auto &s : bit.wire->get_strpool_attribute(ID::src))
 							entry.src.insert(s);
 						entry.wire = bit.wire->name;
 						entry.wirebit = bit.offset;
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 436ac1b01..8ae572ad1 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -675,9 +675,9 @@ struct SatHelper
 		strftime(stime, sizeof(stime), "%c", now);
 
 		std::string module_fname = "unknown";
-		auto apos = module->attributes.find("\\src");
+		auto apos = module->attributes.find(ID::src);
 		if(apos != module->attributes.end())
-			module_fname = module->attributes["\\src"].decode_string();
+			module_fname = module->attributes[ID::src].decode_string();
 
 		fprintf(f, "$date\n");
 		fprintf(f, "    %s\n", stime);
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index d5634b26d..c3e84ead5 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -303,19 +303,19 @@ struct SimInstance
 			RTLIL::SigSpec sig_a, sig_b, sig_c, sig_d, sig_s, sig_y;
 			bool has_a, has_b, has_c, has_d, has_s, has_y;
 
-			has_a = cell->hasPort("\\A");
-			has_b = cell->hasPort("\\B");
+			has_a = cell->hasPort(ID::A);
+			has_b = cell->hasPort(ID::B);
 			has_c = cell->hasPort("\\C");
 			has_d = cell->hasPort("\\D");
-			has_s = cell->hasPort("\\S");
-			has_y = cell->hasPort("\\Y");
+			has_s = cell->hasPort(ID::S);
+			has_y = cell->hasPort(ID::Y);
 
-			if (has_a) sig_a = cell->getPort("\\A");
-			if (has_b) sig_b = cell->getPort("\\B");
+			if (has_a) sig_a = cell->getPort(ID::A);
+			if (has_b) sig_b = cell->getPort(ID::B);
 			if (has_c) sig_c = cell->getPort("\\C");
 			if (has_d) sig_d = cell->getPort("\\D");
-			if (has_s) sig_s = cell->getPort("\\S");
-			if (has_y) sig_y = cell->getPort("\\Y");
+			if (has_s) sig_s = cell->getPort(ID::S);
+			if (has_y) sig_y = cell->getPort(ID::Y);
 
 			if (shared->debug)
 				log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type));
@@ -505,10 +505,10 @@ struct SimInstance
 		for (auto cell : formal_database)
 		{
 			string label = log_id(cell);
-			if (cell->attributes.count("\\src"))
-				label = cell->attributes.at("\\src").decode_string();
+			if (cell->attributes.count(ID::src))
+				label = cell->attributes.at(ID::src).decode_string();
 
-			State a = get_state(cell->getPort("\\A"))[0];
+			State a = get_state(cell->getPort(ID::A))[0];
 			State en = get_state(cell->getPort("\\EN"))[0];
 
 			if (cell->type == "$cover" && en == State::S1 && a != State::S1)