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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
| commit | c094c53de83707a5bf1b268640283f1dde235873 (patch) | |
| tree | 27e480f63e0d34d8cbfcf8fcf29472c198381296 /passes/sat | |
| parent | 8fd8e4a468fb650fe5dcbe892c07010f627e2c2b (diff) | |
| download | yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.gz yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.bz2 yosys-c094c53de83707a5bf1b268640283f1dde235873.zip | |
Removed RTLIL::SigSpec::optimize()
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/eval.cc | 3 | ||||
| -rw-r--r-- | passes/sat/freduce.cc | 10 | ||||
| -rw-r--r-- | passes/sat/sat.cc | 5 |
3 files changed, 5 insertions, 13 deletions
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 9b8c35361..6949b76db 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -53,8 +53,6 @@ struct BruteForceEquivChecker return; } - inputs.optimize(); - ConstEval ce1(mod1), ce2(mod2); ce1.set(mod1_inputs, inputs.as_const()); ce2.set(mod2_inputs, inputs.as_const()); @@ -482,7 +480,6 @@ struct EvalPass : public Pass { RTLIL::SigSpec signal, value, undef; if (!RTLIL::SigSpec::parse_sel(signal, design, module, it)) log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str()); - signal.optimize(); value = signal; if (set_undef) { while (!ce.eval(value, undef)) { diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 1e47e7de2..ba01bc322 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -349,7 +349,7 @@ struct PerformReduction std::vector<RTLIL::SigBit> bucket_sigbits; for (int idx : bucket) bucket_sigbits.push_back(out_bits[idx]); - log("%s Trying to shatter bucket with %d signals: %s\n", indt, int(bucket.size()), log_signal(RTLIL::SigSpec(bucket_sigbits).optimized())); + log("%s Trying to shatter bucket with %d signals: %s\n", indt, int(bucket.size()), log_signal(bucket_sigbits)); } std::vector<int> sat_set_list, sat_clr_list; @@ -494,7 +494,7 @@ struct PerformReduction std::vector<RTLIL::SigBit> r_sigbits; for (int idx : r) r_sigbits.push_back(out_bits[idx]); - log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(RTLIL::SigSpec(r_sigbits).optimized())); + log(" Found group of %d equivialent signals: %s\n", int(r.size()), log_signal(r_sigbits)); } std::vector<int> undef_slaves; @@ -640,7 +640,7 @@ struct FreduceWorker found_selected_wire: log(" Finding reduced input cone for signal batch %s%c\n", - log_signal(RTLIL::SigSpec(std::vector<RTLIL::SigBit>(batch.begin(), batch.end())).optimized()), verbose_level ? ':' : '.'); + log_signal(batch), verbose_level ? ':' : '.'); FindReducedInputs infinder(sigmap, drivers); for (auto &bit : batch) { @@ -663,12 +663,12 @@ struct FreduceWorker continue; if (bucket.first.size() == 0) { - log(" Finding const values for bucket %s%c\n", log_signal(RTLIL::SigSpec(bucket.second).optimized()), verbose_level ? ':' : '.'); + log(" Finding const values for bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.'); PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size()); for (size_t idx = 0; idx < bucket.second.size(); idx++) worker.analyze_const(equiv, idx); } else { - log(" Trying to shatter bucket %s%c\n", log_signal(RTLIL::SigSpec(bucket.second).optimized()), verbose_level ? ':' : '.'); + log(" Trying to shatter bucket %s%c\n", log_signal(bucket.second), verbose_level ? ':' : '.'); PerformReduction worker(sigmap, drivers, inv_pairs, bucket.second, bucket.first.size()); worker.analyze(equiv, 100 * bucket_count / (buckets.size() + 1)); } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 34becaee8..4b6b1b719 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -114,10 +114,6 @@ struct SatHelper } } - lhs.optimize(); - rhs.optimize(); - removed_bits.optimize(); - if (removed_bits.size()) log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits)); @@ -152,7 +148,6 @@ struct SatHelper if (!satgen.initial_state.check_all(big_lhs)) { RTLIL::SigSpec rem = satgen.initial_state.remove(big_lhs); - rem.optimize(); log_cmd_error("Found -set-init bits that are not part of the initial_state: %s\n", log_signal(rem)); } |