SigSpec refactoring: renamed chunks and width to __chunks and __width

6 files changed, 84 insertions, 84 deletions

diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index 5c38cc2cf..5369617be 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -44,7 +44,7 @@ struct BruteForceEquivChecker
 
 	void run_checker(RTLIL::SigSpec &inputs)
 	{
-		if (inputs.width < mod1_inputs.width) {
+		if (inputs.__width < mod1_inputs.__width) {
 			RTLIL::SigSpec inputs0 = inputs, inputs1 = inputs;
 			inputs0.append(RTLIL::Const(0, 1));
 			inputs1.append(RTLIL::Const(1, 1));
@@ -71,9 +71,9 @@ struct BruteForceEquivChecker
 
 		if (ignore_x_mod1) {
 			sig1.expand(), sig2.expand();
-			for (size_t i = 0; i < sig1.chunks.size(); i++)
-				if (sig1.chunks.at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
-					sig2.chunks.at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
+			for (size_t i = 0; i < sig1.__chunks.size(); i++)
+				if (sig1.__chunks.at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
+					sig2.__chunks.at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
 			sig1.optimize(), sig2.optimize();
 		}
 
@@ -172,11 +172,11 @@ struct VlogHammerReporter
 			log_error("Failed to find solution to SAT problem.\n");
 
 		expected_y.expand();
-		for (int i = 0; i < expected_y.width; i++) {
+		for (int i = 0; i < expected_y.__width; i++) {
 			RTLIL::State solution_bit = y_values.at(i) ? RTLIL::State::S1 : RTLIL::State::S0;
-			RTLIL::State expected_bit = expected_y.chunks.at(i).data.bits.at(0);
+			RTLIL::State expected_bit = expected_y.__chunks.at(i).data.bits.at(0);
 			if (model_undef) {
-				if (y_values.at(expected_y.width+i))
+				if (y_values.at(expected_y.__width+i))
 					solution_bit = RTLIL::State::Sx;
 			} else {
 				if (expected_bit == RTLIL::State::Sx)
@@ -184,17 +184,17 @@ struct VlogHammerReporter
 			}
 			if (solution_bit != expected_bit) {
 				std::string sat_bits, rtl_bits;
-				for (int k = expected_y.width-1; k >= 0; k--) {
-					if (model_undef && y_values.at(expected_y.width+k))
+				for (int k = expected_y.__width-1; k >= 0; k--) {
+					if (model_undef && y_values.at(expected_y.__width+k))
 						sat_bits += "x";
 					else
 						sat_bits += y_values.at(k) ? "1" : "0";
-					rtl_bits += expected_y.chunks.at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" :
-							expected_y.chunks.at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0";
+					rtl_bits += expected_y.__chunks.at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" :
+							expected_y.__chunks.at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0";
 				}
 				log_error("Found error in SAT model: y[%d] = %s, should be %s:\n   SAT: %s\n   RTL: %s\n        %*s^\n",
 						int(i), log_signal(solution_bit), log_signal(expected_bit),
-						sat_bits.c_str(), rtl_bits.c_str(), expected_y.width-i-1, "");
+						sat_bits.c_str(), rtl_bits.c_str(), expected_y.__width-i-1, "");
 			}
 		}
 
@@ -203,16 +203,16 @@ struct VlogHammerReporter
 			std::vector<int> cmp_vars;
 			std::vector<bool> cmp_vals;
 
-			std::vector<bool> y_undef(y_values.begin() + expected_y.width, y_values.end());
+			std::vector<bool> y_undef(y_values.begin() + expected_y.__width, y_values.end());
 
-			for (int i = 0; i < expected_y.width; i++)
+			for (int i = 0; i < expected_y.__width; i++)
 				if (y_undef.at(i))
 				{
 					log("    Toggling undef bit %d to test undef gating.\n", i);
 					if (!ez.solve(y_vec, y_values, ez.IFF(y_vec.at(i), y_values.at(i) ? ez.FALSE : ez.TRUE)))
 						log_error("Failed to find solution with toggled bit!\n");
 
-					cmp_vars.push_back(y_vec.at(expected_y.width + i));
+					cmp_vars.push_back(y_vec.at(expected_y.__width + i));
 					cmp_vals.push_back(true);
 				}
 				else
@@ -220,7 +220,7 @@ struct VlogHammerReporter
 					cmp_vars.push_back(y_vec.at(i));
 					cmp_vals.push_back(y_values.at(i));
 
-					cmp_vars.push_back(y_vec.at(expected_y.width + i));
+					cmp_vars.push_back(y_vec.at(expected_y.__width + i));
 					cmp_vals.push_back(false);
 				}
 
@@ -283,7 +283,7 @@ struct VlogHammerReporter
 				while (!ce.eval(sig, undef)) {
 					// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef));
 					log("Warning: Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
-					ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.width));
+					ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.__width));
 				}
 
 				log("++VAL++ %d %s %s #\n", idx, module_name.c_str(), sig.as_const().as_string().c_str());
@@ -293,13 +293,13 @@ struct VlogHammerReporter
 					rtl_sig.expand();
 					sat_check(module, recorded_set_vars, recorded_set_vals, sig, false);
 					sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
-				} else if (rtl_sig.width > 0) {
+				} else if (rtl_sig.__width > 0) {
 					sig.expand();
-					if (rtl_sig.width != sig.width)
+					if (rtl_sig.__width != sig.__width)
 						log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
-					for (int i = 0; i < sig.width; i++)
-						if (rtl_sig.chunks.at(i).data.bits.at(0) == RTLIL::State::Sx)
-							sig.chunks.at(i).data.bits.at(0) = RTLIL::State::Sx;
+					for (int i = 0; i < sig.__width; i++)
+						if (rtl_sig.__chunks.at(i).data.bits.at(0) == RTLIL::State::Sx)
+							sig.__chunks.at(i).data.bits.at(0) = RTLIL::State::Sx;
 				}
 
 				log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str());
@@ -350,7 +350,7 @@ struct VlogHammerReporter
 			}
 			if (!RTLIL::SigSpec::parse(sig, NULL, pattern) || !sig.is_fully_const())
 				log_error("Failed to parse pattern %s!\n", pattern.c_str());
-			if (sig.width < total_input_width)
+			if (sig.__width < total_input_width)
 				log_error("Pattern %s is to short!\n", pattern.c_str());
 			patterns.push_back(sig.as_const());
 			if (invert_pattern) {
@@ -470,9 +470,9 @@ struct EvalPass : public Pass {
 				log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str());
 			if (!rhs.is_fully_const())
 				log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str());
-			if (lhs.width != rhs.width)
+			if (lhs.__width != rhs.__width)
 				log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
-						it.first.c_str(), log_signal(lhs), lhs.width, it.second.c_str(), log_signal(rhs), rhs.width);
+						it.first.c_str(), log_signal(lhs), lhs.__width, it.second.c_str(), log_signal(rhs), rhs.__width);
 			ce.set(lhs, rhs.as_const());
 		}
 
@@ -493,7 +493,7 @@ struct EvalPass : public Pass {
 				if (set_undef) {
 					while (!ce.eval(value, undef)) {
 						log("Failed to evaluate signal %s: Missing value for %s. -> setting to undef\n", log_signal(signal), log_signal(undef));
-						ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.width));
+						ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.__width));
 						undef = RTLIL::SigSpec();
 					}
 					log("Eval result: %s = %s.\n", log_signal(signal), log_signal(value));
@@ -526,15 +526,15 @@ struct EvalPass : public Pass {
 			}
 
 			std::vector<std::string> tab_line;
-			for (auto &c : tabsigs.chunks)
+			for (auto &c : tabsigs.__chunks)
 				tab_line.push_back(log_signal(c));
 			tab_sep_colidx = tab_line.size();
-			for (auto &c : signal.chunks)
+			for (auto &c : signal.__chunks)
 				tab_line.push_back(log_signal(c));
 			tab.push_back(tab_line);
 			tab_line.clear();
 
-			RTLIL::Const tabvals(0, tabsigs.width);
+			RTLIL::Const tabvals(0, tabsigs.__width);
 			do
 			{
 				ce.push();
@@ -548,19 +548,19 @@ struct EvalPass : public Pass {
 								log_signal(tabsigs), log_signal(tabvals), log_signal(this_undef));
 						return;
 					}
-					ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.width));
+					ce.set(this_undef, RTLIL::Const(RTLIL::State::Sx, this_undef.__width));
 					undef.append(this_undef);
 					this_undef = RTLIL::SigSpec();
 				}
 
 				int pos = 0;
-				for (auto &c : tabsigs.chunks) {
+				for (auto &c : tabsigs.__chunks) {
 					tab_line.push_back(log_signal(RTLIL::SigSpec(tabvals).extract(pos, c.width)));
 					pos += c.width;
 				}
 
 				pos = 0;
-				for (auto &c : signal.chunks) {
+				for (auto &c : signal.__chunks) {
 					tab_line.push_back(log_signal(value.extract(pos, c.width)));
 					pos += c.width;
 				}
@@ -602,7 +602,7 @@ struct EvalPass : public Pass {
 			}
 
 			log("\n");
-			if (undef.width > 0) {
+			if (undef.__width > 0) {
 				undef.sort_and_unify();
 				log("Assumend undef (x) value for the following singals: %s\n\n", log_signal(undef));
 			}
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 831a43aa5..4308e7364 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -649,7 +649,7 @@ struct ExposePass : public Pass {
 						{
 							RTLIL::Wire *w = new RTLIL::Wire;
 							w->name = cell->name + sep + RTLIL::unescape_id(it.first);
-							w->width = it.second.width;
+							w->width = it.second.__width;
 							if (ct.cell_input(cell->type, it.first))
 								w->port_output = true;
 							if (ct.cell_output(cell->type, it.first))
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index ac0415644..8cc59b291 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -714,7 +714,7 @@ struct FreduceWorker
 
 				if (grp[i].inverted)
 				{
-					if (inv_sig.width == 0)
+					if (inv_sig.__width == 0)
 					{
 						inv_sig = module->addWire(NEW_ID);
 
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 6e57fceb1..1cd794b56 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -253,11 +253,11 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 		}
 	}
 
-	if (all_conditions.width != 1) {
+	if (all_conditions.__width != 1) {
 		RTLIL::Cell *reduce_cell = new RTLIL::Cell;
 		reduce_cell->name = NEW_ID;
 		reduce_cell->type = "$reduce_and";
-		reduce_cell->parameters["\\A_WIDTH"] = all_conditions.width;
+		reduce_cell->parameters["\\A_WIDTH"] = all_conditions.__width;
 		reduce_cell->parameters["\\Y_WIDTH"] = 1;
 		reduce_cell->parameters["\\A_SIGNED"] = 0;
 		reduce_cell->connections["\\A"] = all_conditions;
@@ -283,8 +283,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 	RTLIL::Cell *not_cell = new RTLIL::Cell;
 	not_cell->name = NEW_ID;
 	not_cell->type = "$not";
-	not_cell->parameters["\\A_WIDTH"] = all_conditions.width;
-	not_cell->parameters["\\A_WIDTH"] = all_conditions.width;
+	not_cell->parameters["\\A_WIDTH"] = all_conditions.__width;
+	not_cell->parameters["\\A_WIDTH"] = all_conditions.__width;
 	not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
 	not_cell->parameters["\\A_SIGNED"] = 0;
 	not_cell->connections["\\A"] = all_conditions;
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index a9a00d8a2..161449324 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -101,10 +101,10 @@ struct SatHelper
 
 			RTLIL::SigSpec lhs = sigmap(it.second);
 			RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
-			log_assert(lhs.width == rhs.width);
+			log_assert(lhs.__width == rhs.__width);
 
 			RTLIL::SigSpec removed_bits;
-			for (int i = 0; i < lhs.width; i++) {
+			for (int i = 0; i < lhs.__width; i++) {
 				RTLIL::SigSpec bit = lhs.extract(i, 1);
 				if (!satgen.initial_state.check_all(bit)) {
 					removed_bits.append(bit);
@@ -118,10 +118,10 @@ struct SatHelper
 			rhs.optimize();
 			removed_bits.optimize();
 
-			if (removed_bits.width)
+			if (removed_bits.__width)
 				log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits));
 
-			if (lhs.width) {
+			if (lhs.__width) {
 				log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
 				big_lhs.remove2(lhs, &big_rhs);
 				big_lhs.append(lhs);
@@ -140,9 +140,9 @@ struct SatHelper
 			show_signal_pool.add(sigmap(lhs));
 			show_signal_pool.add(sigmap(rhs));
 
-			if (lhs.width != rhs.width)
+			if (lhs.__width != rhs.__width)
 				log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
-					s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
+					s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width);
 
 			log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
 			big_lhs.remove2(lhs, &big_rhs);
@@ -166,17 +166,17 @@ struct SatHelper
 			RTLIL::SigSpec rem = satgen.initial_state.export_all();
 			rem.remove(big_lhs);
 			big_lhs.append(rem);
-			big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.width));
+			big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.__width));
 		}
 
 		if (set_init_zero) {
 			RTLIL::SigSpec rem = satgen.initial_state.export_all();
 			rem.remove(big_lhs);
 			big_lhs.append(rem);
-			big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.width));
+			big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.__width));
 		}
 
-		if (big_lhs.width == 0) {
+		if (big_lhs.__width == 0) {
 			log("No constraints for initial state found.\n\n");
 			return;
 		}
@@ -209,9 +209,9 @@ struct SatHelper
 			show_signal_pool.add(sigmap(lhs));
 			show_signal_pool.add(sigmap(rhs));
 
-			if (lhs.width != rhs.width)
+			if (lhs.__width != rhs.__width)
 				log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
-					s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
+					s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width);
 
 			log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
 			big_lhs.remove2(lhs, &big_rhs);
@@ -230,9 +230,9 @@ struct SatHelper
 			show_signal_pool.add(sigmap(lhs));
 			show_signal_pool.add(sigmap(rhs));
 
-			if (lhs.width != rhs.width)
+			if (lhs.__width != rhs.__width)
 				log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
-					s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
+					s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width);
 
 			log("Import set-constraint for this timestep: %s = %s\n", log_signal(lhs), log_signal(rhs));
 			big_lhs.remove2(lhs, &big_rhs);
@@ -358,9 +358,9 @@ struct SatHelper
 				show_signal_pool.add(sigmap(lhs));
 				show_signal_pool.add(sigmap(rhs));
 
-				if (lhs.width != rhs.width)
+				if (lhs.__width != rhs.__width)
 					log_cmd_error("Proof expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
-						s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
+						s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width);
 
 				log("Import proof-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
 				big_lhs.remove2(lhs, &big_rhs);
@@ -386,9 +386,9 @@ struct SatHelper
 				show_signal_pool.add(sigmap(lhs));
 				show_signal_pool.add(sigmap(rhs));
 
-				if (lhs.width != rhs.width)
+				if (lhs.__width != rhs.__width)
 					log_cmd_error("Proof-x expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
-						s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
+						s.first.c_str(), log_signal(lhs), lhs.__width, s.second.c_str(), log_signal(rhs), rhs.__width);
 
 				log("Import proof-x-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
 				big_lhs.remove2(lhs, &big_rhs);
@@ -413,8 +413,8 @@ struct SatHelper
 			satgen.getAsserts(asserts_a, asserts_en, timestep);
 			asserts_a.expand();
 			asserts_en.expand();
-			for (size_t i = 0; i < asserts_a.chunks.size(); i++)
-				log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.chunks[i]), log_signal(asserts_en.chunks[i]));
+			for (size_t i = 0; i < asserts_a.__chunks.size(); i++)
+				log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.__chunks[i]), log_signal(asserts_en.__chunks[i]));
 			prove_bits.push_back(satgen.importAsserts(timestep));
 		}
 
@@ -543,12 +543,12 @@ struct SatHelper
 
 		std::vector<int> modelUndefExpressions;
 
-		for (auto &c : modelSig.chunks)
+		for (auto &c : modelSig.__chunks)
 			if (c.wire != NULL)
 			{
 				ModelBlockInfo info;
 				RTLIL::SigSpec chunksig = c;
-				info.width = chunksig.width;
+				info.width = chunksig.__width;
 				info.description = log_signal(chunksig);
 
 				for (int timestep = -1; timestep <= max_timestep; timestep++)
@@ -573,7 +573,7 @@ struct SatHelper
 		// Add initial state signals as collected by satgen
 		//
 		modelSig = satgen.initial_state.export_all();
-		for (auto &c : modelSig.chunks)
+		for (auto &c : modelSig.__chunks)
 			if (c.wire != NULL)
 			{
 				ModelBlockInfo info;
@@ -581,7 +581,7 @@ struct SatHelper
 
 				info.timestep = 0;
 				info.offset = modelExpressions.size();
-				info.width = chunksig.width;
+				info.width = chunksig.__width;
 				info.description = log_signal(chunksig);
 				modelInfo.insert(info);
 
diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index 42e59c475..95f35bb3e 100644
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -273,11 +273,11 @@ struct ShareWorker
 			RTLIL::SigSpec a2 = c2->connections.at("\\A");
 			RTLIL::SigSpec y2 = c2->connections.at("\\Y");
 
-			int a_width = std::max(a1.width, a2.width);
-			int y_width = std::max(y1.width, y2.width);
+			int a_width = std::max(a1.__width, a2.__width);
+			int y_width = std::max(y1.__width, y2.__width);
 
-			if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
-			if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
+			if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
+			if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
 
 			RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
 			RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
@@ -292,8 +292,8 @@ struct ShareWorker
 			supercell->connections["\\Y"] = y;
 			module->add(supercell);
 
-			RTLIL::SigSpec new_y1(y, y1.width);
-			RTLIL::SigSpec new_y2(y, y2.width);
+			RTLIL::SigSpec new_y1(y, y1.__width);
+			RTLIL::SigSpec new_y2(y, y2.__width);
 
 			module->connections.push_back(RTLIL::SigSig(y1, new_y1));
 			module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@@ -367,28 +367,28 @@ struct ShareWorker
 			RTLIL::SigSpec b2 = c2->connections.at("\\B");
 			RTLIL::SigSpec y2 = c2->connections.at("\\Y");
 
-			int a_width = std::max(a1.width, a2.width);
-			int b_width = std::max(b1.width, b2.width);
-			int y_width = std::max(y1.width, y2.width);
+			int a_width = std::max(a1.__width, a2.__width);
+			int b_width = std::max(b1.__width, b2.__width);
+			int y_width = std::max(y1.__width, y2.__width);
 
 			if (c1->type == "$shr" && a_signed)
 			{
 				a_width = std::max(y_width, a_width);
 
-				if (a1.width < y1.width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.width), true)->connections.at("\\Y");
-				if (a2.width < y2.width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.width), true)->connections.at("\\Y");
+				if (a1.__width < y1.__width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.__width), true)->connections.at("\\Y");
+				if (a2.__width < y2.__width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.__width), true)->connections.at("\\Y");
 
-				if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
-				if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
+				if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
+				if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections.at("\\Y");
 			}
 			else
 			{
-				if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
-				if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
+				if (a1.__width != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
+				if (a2.__width != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections.at("\\Y");
 			}
 
-			if (b1.width != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
-			if (b2.width != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
+			if (b1.__width != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
+			if (b2.__width != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections.at("\\Y");
 
 			RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
 			RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act);
@@ -405,8 +405,8 @@ struct ShareWorker
 			supercell->connections["\\Y"] = y;
 			supercell->check();
 
-			RTLIL::SigSpec new_y1(y, y1.width);
-			RTLIL::SigSpec new_y2(y, y2.width);
+			RTLIL::SigSpec new_y1(y, y1.__width);
+			RTLIL::SigSpec new_y2(y, y2.__width);
 
 			module->connections.push_back(RTLIL::SigSig(y1, new_y1));
 			module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@@ -575,7 +575,7 @@ struct ShareWorker
 		if (activation_patterns_cache[cell].empty()) {
 			log("%sFound cell that is never activated: %s\n", indent, log_id(cell));
 			RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell];
-			module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.width)));
+			module->connections.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.__width)));
 			cells_to_remove.insert(cell);
 		}
 
@@ -811,10 +811,10 @@ struct ShareWorker
 				int other_cell_select_score = 0;
 
 				for (auto &p : filtered_cell_activation_patterns)
-					cell_select_score += p.first.width;
+					cell_select_score += p.first.__width;
 
 				for (auto &p : filtered_other_cell_activation_patterns)
-					other_cell_select_score += p.first.width;
+					other_cell_select_score += p.first.__width;
 
 				RTLIL::Cell *supercell;
 				if (cell_select_score <= other_cell_select_score) {