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| author | clairexen <claire@symbioticeda.com> | 2020-09-29 17:31:01 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-09-29 17:31:01 +0200 |
| commit | 7b9a93aa2e455de499f8ddccf19507f5e932dd42 (patch) | |
| tree | 48c22225727f0cc1e7d3efd19c78317c87296cc0 /passes/sat | |
| parent | e8c9e541a735894a974aaebfb88dfaa9aa3e0f31 (diff) | |
| parent | dc4a6176945618a40960fdd79ecfa2a8ef104487 (diff) | |
| download | yosys-7b9a93aa2e455de499f8ddccf19507f5e932dd42.tar.gz yosys-7b9a93aa2e455de499f8ddccf19507f5e932dd42.tar.bz2 yosys-7b9a93aa2e455de499f8ddccf19507f5e932dd42.zip | |
Merge pull request #2393 from nakengelhardt/no_const_sensitivity
write_verilog: emit intermediate wire for constant values in sensitivity list
Diffstat (limited to 'passes/sat')
0 files changed, 0 insertions, 0 deletions