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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:48:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:48:45 -0700 |
| commit | 4c9fde87d170fc8d4b729581b055407553951e4c (patch) | |
| tree | 6213f8f04492f2868737a4a8348abfd07e0f7c80 /passes/sat | |
| parent | 2dffa4685b830313204f5d04314a14ed6ecac8ec (diff) | |
| download | yosys-4c9fde87d170fc8d4b729581b055407553951e4c.tar.gz yosys-4c9fde87d170fc8d4b729581b055407553951e4c.tar.bz2 yosys-4c9fde87d170fc8d4b729581b055407553951e4c.zip | |
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
This reverts commit 2dffa4685b830313204f5d04314a14ed6ecac8ec.
Diffstat (limited to 'passes/sat')
0 files changed, 0 insertions, 0 deletions