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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:13:33 -0700 |
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committer | GitHub <noreply@github.com> | 2020-04-02 07:13:33 -0700 |
commit | 37f42fe102e329793b884a47321423062eedfce7 (patch) | |
tree | 42cca1494ce7d806e8a638fe56bc8acd13733a21 /passes/sat | |
parent | 347774945972dc71910a3e38c9ec678f74f97d03 (diff) | |
parent | 348e8923148f1cc1bfb87bb71b7566d4bc111704 (diff) | |
download | yosys-37f42fe102e329793b884a47321423062eedfce7.tar.gz yosys-37f42fe102e329793b884a47321423062eedfce7.tar.bz2 yosys-37f42fe102e329793b884a47321423062eedfce7.zip |
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
kernel: speedup by using more pass-by-const-ref
Diffstat (limited to 'passes/sat')
-rw-r--r-- | passes/sat/clk2fflogic.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index f9e7783a9..24aba22f3 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -117,11 +117,11 @@ struct Clk2fflogicPass : public Pass { SigSpec clock_edge_pattern; if (clkpol) { - clock_edge_pattern.append_bit(State::S0); - clock_edge_pattern.append_bit(State::S1); + clock_edge_pattern.append(State::S0); + clock_edge_pattern.append(State::S1); } else { - clock_edge_pattern.append_bit(State::S1); - clock_edge_pattern.append_bit(State::S0); + clock_edge_pattern.append(State::S1); + clock_edge_pattern.append(State::S0); } SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern); @@ -257,11 +257,11 @@ struct Clk2fflogicPass : public Pass { SigSpec clock_edge_pattern; if (clkpol) { - clock_edge_pattern.append_bit(State::S0); - clock_edge_pattern.append_bit(State::S1); + clock_edge_pattern.append(State::S0); + clock_edge_pattern.append(State::S1); } else { - clock_edge_pattern.append_bit(State::S1); - clock_edge_pattern.append_bit(State::S0); + clock_edge_pattern.append(State::S1); + clock_edge_pattern.append(State::S0); } SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern); |