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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-22 18:03:06 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-22 18:03:06 +0100 |
| commit | a440f82586eda461ae2a90cba7a14d7078c41f37 (patch) | |
| tree | 10eb988328a6301110c6194aa763fb318938e664 /passes/sat/mutate.cc | |
| parent | 7d8d0d0155d46d30d21d95325df7f99b36058a96 (diff) | |
| parent | 638be461c3a6d33aa294700249ee0bc27da69403 (diff) | |
| download | yosys-a440f82586eda461ae2a90cba7a14d7078c41f37.tar.gz yosys-a440f82586eda461ae2a90cba7a14d7078c41f37.tar.bz2 yosys-a440f82586eda461ae2a90cba7a14d7078c41f37.zip | |
Merge pull request #889 from YosysHQ/clifford/fix888
Fix mem2reg handling of memories with upto data ports
Diffstat (limited to 'passes/sat/mutate.cc')
0 files changed, 0 insertions, 0 deletions