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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-01-17 12:58:08 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2023-01-17 12:58:08 +0100 |
| commit | 6574553189fb6ccb5d00a0c043671a625672b3d3 (patch) | |
| tree | 57e3212ee75493d9f4939c9f9029b95880367a76 /passes/proc | |
| parent | 956c4e485a9463863f60c4dd03372db3fa8332a4 (diff) | |
| download | yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.tar.gz yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.tar.bz2 yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.zip | |
Fixes for some of clang scan-build detected issues
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_dff.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 234671df5..fd56786f2 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -302,7 +302,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) ce.assign_map.apply(rstval); ce.assign_map.apply(sig); - if (rstval == sig) { + if (rstval == sig && sync_level) { if (sync_level->type == RTLIL::SyncType::ST1) insig = mod->Mux(NEW_ID, insig, sig, sync_level->signal); else |